Intel Corporation

Micron Technology Incorporated

Jaydip Bharatkumar Patel

Balaji Srinivasan

Ashraf B Islam

Mark Alan Helm

Max F Hineman

Khaled Hasnat

Matthew Goldman

Yasir Mohsin Husain

Nicolas L Irizarry

Everardo Flores, Iii

Thomas F Ryan

A method, apparatus and system. The method includes: generating a feedback voltage Vin a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vat said one of the BL or WL; generating, in a reference circuit, one of a reference voltage Vto track a feedback voltage of the feedback circuit or a mirror current Ito track a current Ithrough said each of the memory cells; and providing one of values for both Vand V, or for an output voltage Vcorresponding to I, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of Vwith Vor based on V.

Apparatus, system and method to sense a logic state of a memory cell in a three-dimensional memory device

A method, memory device and system. The memory device includes an active memory array including memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs; a dummy array including dummy address lines, the dummy address lines including dummy BLs and dummy WLs; at least one shorting structure extending across and in electrical contact with at least some of the dummy address lines to electrically short the at least some of the dummy address lines together; and at least one contact structure extending from the dummy array and electrically coupled to the at least some of the dummy address lines to connect the at least some of the dummy address lines to a predetermined voltage.

Memory array with shorting structure on a dummy array thereof, and method of providing same

A sensing circuit for sensing an analog signal includes a level shifter that shifts the analog signal from a high voltage domain to a low voltage domain. The signal originates from the high voltage domain, and is passed to the low voltage domain through the level shifter. A source line provides the analog signal, which can be selectively switched into a sense amplifier circuit. The sense amplifier is in the low voltage domain and generates a digital output to represent the sensed analog signal.

Low voltage, low power sensing based on level shifting sensing circuit

Devices and methods facilitate memory device operation in all bit line architecture memory devices. In at least one embodiment, memory cells comprising alternating rows are concurrently programmed by row and concurrently sensed by row at a first density whereas memory cells comprising different alternating rows are concurrently programmed by row and concurrently sensed by row at a second density. In at least one additional embodiment, memory cells comprising alternating tiers of memory cells are programmed and sensed by tier at a first density and memory cells comprising different alternating tiers of memory cells are programmed and sensed by tier at a second density.

Memory devices and operating methods for a memory device

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Folsom, CA, United States of America

Jaydip Bharatkumar Patel