Texas Instruments Corporation

Jayawardan Janardhanan

Deric Wayne Waters

Goutam Dutta

Christopher Andrew Schell

Sinjeet Parekh

Subhashish Mukherjee

Sandeep Rao

Yogesh Darwhekar

Saket Thukral

Arvind Sridhar

Jaiganesh Balakrishnan

Sujoy Chakravarty

Eric Paul Lindgren

Varun Tripuraneni

Karthik Subburaj

Anant Shankar Kamath

Sthanunathan Ramakrishnan

Krishnaswamy Thiagarajan

Jagdish Chand Goyal

Samala Sreekiran

Henry Yao

Vikas Kumar Sinha

Robert Bogdan Staszewski

Tarkesh Pande

Karthik Ramasubramanian

Jawaharlal Tangudu

Khurram Waheed

Krishnaswamy Nagaraj

Sriram Murali

Sarma Sundareswara Gunturi

Raghu Ganesan

Debapriya Sahu

Saket Jalan

Vineet Mishra

Srikanth Manian

Meghna Agrawal

Sameh Sameer Rezeq

Pranav Kumar

Arpan Sureshbhai Thakkar

Sachin Bhardwaj

Sudheer Kumar Vemulapalli

Srinivas Theertham

Deepak Mohanlal Khanchandani

Jagdish Chand

Somasunder Kattepura Sreenath

Apoorva Bhatia

Gopalkrishna Nayak

Uday Kiran Meda

Shivaprakash Halagur

Yogesh Shekar

Ramanujam Thodur Madabusi

A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.

Systems and methods for online gain calibration of digital-to-time converters

A system () for pedestrian use includes an accelerometer () having multiple electronic sensors; an electronic circuit () operable to generate a signal stream representing magnitude of overall acceleration sensed by the accelerometer (), and to electronically correlate a sliding window () of the signal stream with itself to produce peaks at least some of which represent walking steps, and further operable to electronically execute a periodicity check () to compare different step periods for similarity, and if sufficiently similar then to update () a portion of the circuit substantially representing a walking-step count; and an electronic display () responsive to the electronic circuit () to display information at least in part based on the step count. Other systems, electronic circuits and processes are disclosed.

Robust step detection using low cost MEMS accelerometer in mobile applications, and processing methods, apparatus and systems

A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.

Dual slope digital-to-time converters and methods for calibrating the same

A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

Frequency synthesizer

A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.

Cycle slip detection and correction in phase-locked loop

A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

Phase cancellation in a phase-locked loop

A system comprises a plurality of sensors, a sensor processor, and a sampling rate engine. The sensor processor is coupled to an output of each sensor of the plurality of sensors. The sensor processor estimates user dynamics in response to a first output signal of a first sensor of the plurality of sensors. The sampling rate engine is coupled to an output of the sensor processor. The sampling rate engine determines a sampling rate value of a second sensor of the plurality of sensors in response to a user dynamics value from the sensor processor. The second sensor comprises a selectable sampling rate. The selectable sampling rate is configured in response to the sampling rate value determined by the sampling rate engine.

System of power-saving in MEMS sensor applications

A selection circuit receives a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop couples to an output of the selection circuit and uses the selected reference clock for phase locking an output clock. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit receives a separate reference clock. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.

Corrupted clock detection circuit for a phase-locked loop

A circuit includes a time-to-digital converter (TDC) to produce an output signal that is a function of a time difference between a first input clock to the TDC and a second input clock to the TDC. A first delay line is also included to add a time delay to a third clock to produce the first input clock. A pseudo random binary sequence generator generates a pseudo random binary bit sequence to be used to vary the amount of time delay added by the first delay line to the third clock.

Wobble reduction in an integer mode digital phase locked loop

A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.

Crystal oscillator offset trim in a phase-locked loop

A phase-locked loop circuit includes a first time-to-digital converter (TDC) to receive an input reference signal, a digital-controlled oscillator (DCO), and a first divider coupled to an output of the DCO. The first divider divides down a frequency of an output from the DCO. A second divider divides down a frequency of an output form the first divider to provide a second divider output to an input of the first TDC. The first TDC generates an output digital value encoding a time difference between corresponding edges of the input reference signal and the second divider output. A second TDC receives the input reference signal. An averager circuit generates a digital output that is indicative of an average of an output from the second TDC. A subtractor circuit subtracts the digital output from the average and the output digital value from the first TDC.

Digital phase-locked loop

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Bengaluru, India

Jayawardan Janardhanan