International Business Machines Corporation

Jayashri Arsikere Basappa

Anil Pothireddy

David Grant Wheeler

Venkatasreekanth Prudvi

Kenneth Pichamuthu

Gopikrishnan Viswanadhan

Baalaji Ramamoorthy Konda

Neranjen Ramalingam

Sandeep Niranjan Tippannanavar

A method is disclosed that employs a hierarchical path database generator for accessing internal signal or port names in a design hierarchy of an integrated circuit design. The method comprises the steps of inputting design files into the hierarchical path database generator; and said hierarchical path database generator determining ports and signals in said design files, and storing the names of said ports and signals in a hierarchical database in a logical hierarchical order. The method comprises the further steps of providing a testcase to verify a defined aspect of the integrated circuit design; parsing the testcase to identify all signal and port names therein; and for each of the signal and port names identified in the testcase, inputting said each name into the hierarchical path database generator, and obtaining from that generator a hierarchical path associated with said each signal and port name.

Method and system for automatically accessing internal signals or ports in a design hierarchy

A method an apparatus is provided to generate a gray code sequence from a sequence of binary values having a length 'L'. Accordingly, one aspect of the present invention provides a circuit comprising a cycle flag toggle circuit configured to toggle a cycle flag between a first value and a second value, an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value, and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code.

Encoding a gray code sequence for an odd length sequence

A method of in system diagnostics through scan matrix, and an integrated circuit chip in which the diagnostics are performed, are disclosed. The integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry in the integrated circuit chip is tested, the integrated circuit chip comprises a scan matrix controller and an instruction register. The scan matrix controller is provided for partitioning said circuitry into multiple matrices, each of the matrices having a plurality of scan elements. The instruction register is provided for holding instructions for the scan matrix controller for partitioning the chip into said multiple matrices. The scan matrix controller is further arranged to test each of said matrices according to instructions in the instruction register by applying a test signal to the tested part of the circuitry.

In system diagnostics through scan matrix

A technique is disclosed for observing the data movement pattern in a peripheral device attached to a computer communications network data transmission switch, in order to arrive at a (statistical) determination of whether the peripheral device is being used as a 'load intensive' device or as a 'store intensive' device (or as neither type) over a defined time period. This determination is used to dynamically adjust (and re-allocate) the &#x201c;outbound&#x201d; and &#x201c;inbound&#x201d; buffer memory sizes assigned to a switch transmission port attached to the peripheral device, in cases where the device is operating in either &#x201c;load intensive&#x201d; or &#x201c;store intensive&#x201d; mode. The invention is applicable for use with all types of communications network switches (i.e. &#x201c;Bridges&#x201d;, &#x201c;Hubs&#x201d;, &#x201c;Routers&#x201d; etc.).

Efficient load/store buffer memory management in a computer communications network data transmission switch

Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence.

Generating a gray code for an odd length sequence using a virtual space

Generating Gray sequences for non-standard sequence lengths to be used in cyclical sequences having L members. For binary members of the cyclical sequence having values less than L/2 an amount (C/2&#x2212;L) the most significant bit is forced to a logical '1' to create intermediate binary members. For members greater than or equal to an amount (C/2&#x2212;L) is added to the binary to create intermediate binaries. The intermediate binaries are then transformed to a Gray code sequence having a non-standard sequence length of L.

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Karnataka, India

Jayashri Arsikere Basappa