Texas Instruments Corporation

Anora, LLC

Jayashree Saxena

Lee Doyle Whetsel

Kenneth Michael Butler

Pramodchandran Variyam

John Michael Carulli, Jr

Hari Balachandran

Alessandro Paglieri

Venugopal Puvvada

Matthew Craig Bullock

Atul Kumar Jain

Amit P Vasavada

Jeremy Lee

Ken Butler

An example method for determining test conditions for at-speed transition delay fault tests on semiconductor devices is provided and includes analyzing scan patterns for testing a circuit of a device-under-test (DUT), identifying paths in the circuit activated by the scan patterns, determining behavior of the paths at different test corners, generating a histogram for each scan pattern representing a distribution of paths exhibiting worst-case behavior at corresponding test corners, generating an ordered set of scan pattern-test corner combinations based on the histogram, selecting a threshold for the ordered scan pattern-test corner combinations based on quality metrics, generating an ordered test set including the ordered scan pattern-test corner combinations with the selected threshold, and feeding the ordered test set to a test instrument, the test instrument testing the DUT according to the ordered test set, the tests being performed at the test corners listed above the selected threshold.

Determining test conditions for at-speed transition delay fault tests on semiconductor devices

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Automatable scan partitioning for low power using external control

Decoder providing separate clock and enable for scan path segments

Decode logic driving segmented scan cells with clocks and enables

Divided scan path segments maintaining test pattern of stimulus/response connections

A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of interest associated with a portion of an integrated circuit (IC) die. In one embodiment the method includes the step of: estimating a test escape rate for a set of fault tests to be performed on an IC under design based on an estimated yield and a combined coverage of the set of fault tests; the combined coverage accounting for overlapping coverage among the set of fault tests.

System and method for estimating test escapes in integrated circuits

Disclosed herein is a massive multi-site (MMS) testing architecture. The MMS architecture includes a MMS interface on each of a plurality of devices under test. The MMS interface includes a test protocol manager that may receive test stimulus and send the test stimulus to cores of the device under test. The test protocol manager may receive test responses from cores of the device under test and generate test comparisons based on comparisons between the test responses and expected responses. The test protocol manager may store the test comparisons on the device under test and communicate the stored test comparisons to automated test equipment (ATE) upon being queried by the ATE. The device under test may send the test comparisons to the ATE over a low-bandwidth communication.

Test protocol manager for massive multi-site test

A timing closure analysis associated with SoCs uses voltage drop based standard delay formats (SDFs). Static timing analysis (STA) is implemented using multiple SDFs, one for each mode (ATPG Test, BIST Test, Functional) as contrasted with doing STA with only one worst-case SDF for all modes. The multiple SDFs account for the impact of dynamic voltage drops on delays in addition to static IR drops.

Timing closure for system on a chip using voltage drop based standard delay formats

Decode logic selecting IC scan path parts

A low power scan architecture is formed of a conventional scan architecture. The conventional scan path is divided into equal parts and each part is operated in sequence. An adaptor receives the conventional shift and capture control siqnals from a conventional tester and provides separate shift and capture control siqnals for each of the scan path parts. The adaptor also receives additional select control siqnals from the tester for selecting operation of individual ones of the scan path parts. The disclosed architecture reduces power consumption during testing by a fraction representing the number of equal parts, while maintaining the same test time.

Divided scan path with decode logic receiving select control signals

A system for generating a pruned diagnostic list of potential bridging faults in a circuit includes a pattern generator operable to generate test patterns for testing a circuit and a tester in communication with the pattern generator that is operable to apply the test patterns to the circuit and generate a plurality of resultant vectors. The system also includes a stuck-at fault dictionary including a list of a plurality of nets of the circuit, each net having at least one resultant vector that indicates a potential stuck-at fault at the net. The system further includes a test analysis tool in communication with the pattern generator and the tester, the test analysis tool operable to create an initial logical diagnostic list of tested nets of the circuit associated with the potential stuck-at faults indicated in the stuck-at fault dictionary, the initial logical diagnostic list created in response to the generated plurality of resultant vectors. The system also includes a diagnostic tool in communication with the test analysis tool and the tester, the diagnostic tool operable to create a final logical diagnostic list using the resultant vectors, stuck-at fault dictionary, and the initial logical diagnostic list, the final logical diagnostic list having a plurality of potential bridging faults ranked in order of logical probability.

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Richardson, TX, United States of America

Jayashree Saxena