Intel Corporation

Jayashree Kar

David Gregory Figueroa

Srikrishnan Venkataraman

Yuan-Liang Li

Dong Zhong

Michael M DeSmith

Muhammed Elgousi

Sudarshan D Solanki

Priyavadan Ramdas Patel

Method and apparatus to control delay between lanes in an I/O interface is disclosed. To control the delay between the lanes in the I/O system a programmed delay may be determined and introduced between the lanes. For this purpose the effective time 'T' of the lanes is determined. The number of lanes 'N' in the I/O interface is identified. The programmed lane to lane delay &#x201c;D&#x201d; is determined and a delay circuit having the programmed delay may be introduced between the lanes to reduce AC peak to peak noise in the I/O system.

Method to control delay between lanes

A noise reduction method by implementing certain point-to-point delay is disclosed. In this regard a method is introduced comprising determining a frequency of a greatest noise on a high-speed data link when turning on a power delivery network, determining a delay time between a first port and a second port that minimizes the greatest noise, and turning on the second port after the delay time from turning on the first port. Other embodiments are also disclosed and claimed.

Noise reduction method by implementing certain port-to-port delay

A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.

Power plane to reduce voltage difference between connector power pins

Growing community of inventors

Saratoga, CA, United States of America

Jayashree Kar