Lsi Logic Corporation

Lsi Corporation

Jayashree Kalpathy-Cramer

Eric J Kirchner

Michael J Berman

David T Price

Mark Ward

Thomas Frederick Bibby, Jr

A method for verifying that a physical location of a memory matches a design logical representation, without having to use a focused ion beam to physically damage a memory location. The method provides that either a temporary or permanent circuit 'defect' is intentionally created in the physical layout. Then, the new electrical schematic is extracted from the modified physical layout. Subsequently, if the design 'defect' which was created is temporary, the new electrical schematic is simulated, the logical address of the &#x201c;defect&#x201d; is determined, and the extracted logical address is compared to the expected address to verify the logical to physical correlation. Alternatively, if the design &#x201c;defect&#x201d; which was created is permanent, after the new electrical schematic is extracted from the modified physical layout, the product is fabricated and the known design &#x201c;defect&#x201d; location is used to correlate to the electrically-tested defect logical location.

Method for SRAM bitmap verification

The present invention provides a method for forming interconnect lines and conductors and passive devices in the fabrication of an integrated circuit. A gap is created in the patterning of a first layer. The gap is filled by a dielectric material so that an encapsulated conduit is formed in the gap. The encapsulated conduit is filled with a conductor by chemical vapor deposition processes or other deposition processes, the filling facilitated by forming via holes to intersect the conduit, and then filling the via holes. The conductor filled conduit can be used as a resistor, fuse, inductor, or capacitor.

Microchannel formation for fuses, interconnects, capacitors, and inductors

An apparatus for planarizing a surface of a semiconductor wafer includes a wafer support configured to receive the semiconductor wafer so that the surface of the semiconductor wafer projects from the wafer support. The apparatus also includes a polishing member configured in the form of an endless unitary belt which is devoid of seams. The endless unitary belt is (i) positioned in contact with the surface of the semiconductor wafer and (ii) capable of moving in a linear direction relative to the surface of the semiconductor wafer so as to planarize the surface of the semiconductor wafer. An associated method of linearly planarizing a surface of a semiconductor is also described.

Apparatus and method for linearly planarizing a surface of a semiconductor wafer

A polishing pad surface having a surface designed for chemical mechanical polishing of a substrate surface is described. The polishing pad surface includes a first area on the surface exposed to and capable of contacting a first amount of the substrate surface during chemical-mechanical polishing and a second area on the surface exposed to and capable of contacting a second amount of the substrate surface during chemical-mechanical polishing, wherein the second amount is larger than the first amount of the substrate surface to produce a more uniformly polished substrate surface.

Modifying contact areas of a polishing pad to promote uniform removal rates

A conditioning wafer for conditioning a polishing pad employed in chemical-mechanical polishing of an integrated circuit substrate is described. The conditioning wafer includes a disk having a conditioning surface and a plurality of abrasive particles secured on the conditioning surface of the disk. Furthermore, the abrasive particles engage with the polishing pad when the conditioning wafer contacts the polishing pad during conditioning of the polishing pad.

Chemical-mechanical polishing pad conditioning systems

A process of conditioning a polishing pad used in chemical mechanical polishing of an integrated circuit and having a glazed layer is described. The process includes introducing a conditioning reagent including at least one of hydrofluoric acid, buffered oxide etch composition and potassium hydroxide on the polishing pad to dissolve at least a portion of the glazed layer; and abrading the glazed layer and disloding at least some particles from the glazed layer.

Use of hydrofluoric acid for effective pad conditioning

A post metal chemical-mechanical polishing cleaning process that effectively inhibits corrosion of a metallic plug is described. The process includes providing a partially fabricated integrated circuit (IC) substrate having a metallic plug that is formed by subjecting a metallic surface on the integrated circuit (IC) substrate to chemical-mechanical polishing, which produces a contaminated dielectric layer containing metallic contaminants. The process also includes scrubbing the IC substrate surface in the presence of a mixture including ethylene glycol and hydrofluoric acid to remove at least a portion of the contaminated dielectric layer and to effectively inhibit corrosion of the metallic plug. The mixture has ethylene glycol in an amount that is between about 2 times and about 7 times the amount of hydrofluoric acid.

Use of ethylene glycol as a corrosion inhibitor during cleaning after

A polishing pad surface designed for chemical mechanical polishing of substrates is described. The polishing pad includes a first area of the surface having formed thereon a first set of grooves and a second area of the surface having formed thereon a second set of grooves, wherein the first set of grooves have a larger cross-sectional area than the second set of grooves.

Controlling groove dimensions for enhanced slurry flow

Provided is a chemical mechanical polishing pad having grooves in its polishing surface which have a sub-surface cross-sectional span greater than the grooves' surface opening span. In this way, the edges of the groove are undercut. This provides both increased groove volume for a given pad surface area and groove depth, and variable flexibility in the polishing pad's surface. Grooves in pads of the invention also typically include a neck region at the top of the groove, where the groove side walls are substantially parallel. This provides a margin for the pad to wear during polishing without affecting the pad's surface area. The invention also provides a method and apparatus for cutting grooves in a chemical mechanical polishing pad.

Chemical mechanical polishing pad slurry distribution grooves

A method for determining the thickness of a film in a film stack using reflectance spectroscopy is provided in which one of the films in the stack has unknown optical constants. Conventional methods of using reflectance measurements to determine the thickness of a film require knowledge of the thicknesses and optical constants of all underlying films. An embodiment involves forming a test layer across a substrate having a known thickness and known optical constants. The thickness of the layer is determined using reflectance measurements. A first layer of the same material is then formed across a second layer at the same conditions that the test layer was formed. Thus, the test layer and the first layer can be assumed to have the same thicknesses. A spectral response curve may be determined for the first layer. The first layer is then processed so that its thickness is no longer known. The second layer has unknown optical constants, making it difficult to use reflectance measurements to find the unknown thickness. The values of the unknown optical constants may be guessed and used with the known thickness of unprocessed first layer to create a model spectral response curve. The optical constants may be repeatably varied until the model response curve matches the measured response curve. When this happens, the reasonable optical constants have been found and may be used in determining the thickness of the processed first layer.

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West Linn, OR, United States of America

Jayashree Kalpathy-Cramer