Intel Corporation

Jayasekhar Tholiyil

Malay Trivedi

Sivakumar Radhakrishnan

Christopher P Mozak

Theodore Zale Schoenborn

Mahesh S Natu

Zvika Greenfield

Bruce Querbach

David G Ellis

Bryan L Spry

Anand K Enamandram

Jay Joseph Nejedlo

Tina C Zhong

Philip Abraham

Erik A McShane

Christopher E Yunker

Rony Ghattas

Charles D Lucas

Roger W Liu

An error handling device logs errors in a computing system including a plurality of devices connected to the error handling device. The error handling device provides groups of error registers. Each group of error registers is associated with a value of a plurality of values. Each of the devices that communicate errors to the error handling device are associated with one of the values. The error handling device receives error messages from the devices connected to the error handling device and for each received error message of the received error messages, determines a value of the plurality of values associated with the device transmitting the received error message, determines the group of error registers associated with the determined value, and log the received error message in the determined group of error registers.

Logging errors in error handling devices in a system

Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.

Micro-architectural techniques to minimize companion die firmware loading times in a server platform

REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

Robust memory link testing using memory controller

Growing community of inventors

Hillsboro, OR, United States of America

Jayasekhar Tholiyil