Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Philips Electronics North America Corporation

Vsli Technology, Inc.

Jayarama N Shenoy

Subhas Bothra

Sanjay Dandia

Richard L Wheeler

Paul R Findley

A packaged semiconductor circuit for use in processing digital and RF signals. The packaged semiconductor circuit includes a package structure having a first side that includes a metallization layer. The metallization layer has a first part at about a center of the first side and a second part that surrounds the center. The circuit further includes a semiconductor die that is attached to the package structure at about the first part of the metallization layer. The semiconductor die has an interconnection side including an array of bumps that are configured to make electrical connection to selected ones of a first plurality of metallization traces that are defined in the first part of the metallization layer of the package structure. The circuit also includes a spiral inductor trace that is formed from the metallization layer of the package structure and is defined in the first part of the metallization layer. And, selected ones of the array of bumps are electrically interconnected to a first end of the spiral inductor trace and to a second end of the spiral inductor trace, such that selected ones of the array of bumps electrically interconnect the spiral inductor trace of the package structure to the semiconductor die and to selected ones of the first plurality of metallization traces. Furthermore, spiral inductor that is part of the package structure has a significantly improved quality factor &ldquo;Q&rdquo; and self-resonant frequency compared to a die fabricated inductor.

Method of making an electronic product including package-based inductor coupled to integrated circuit

A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in turn disposed over an active region of a substrate. A pair of shallow trenches are defined on either side of the gate stack, and an intrinsic silicon material is disposed within the pair of shallow trenches up to a top surface of the gate stack. The MOSFET structure further includes source and drain implanted impurities that are defined in an upper portion of the intrinsic silicon material. The upper portion is configured to extend down into the intrinsic silicon material to a target diffusion level that is just below the gate oxide of the gate stack.

Method of making a MOSFET structure having improved source/drain junction performance

High performance chip/package inductor integration

A flip-chip semiconductor device with generic bump patterns formed on a semiconductor substrate and having optimized electrical performance is provided. In a preferred embodiment, the flip-chip semiconductor device includes a semiconductor substrate on which active elements are formed and which has a surface having a plurality of peripheral portions, the active elements including Input/Output (I/O) circuitry and logic circuitry, a first power supply wiring and a first ground wiring disposed in the semiconductor substrate, a signal wiring disposed in the semiconductor substrate, and a first plurality of bumps arranged on the plurality of peripheral portions and selectively used for coupling the semiconductor substrate to a second substrate. The first plurality of bumps are arranged in a matrix pattern of 6 rows by n columns. Bumps in predetermined locations in the matrix are selectively coupled to the first power supply wiring and the first ground wiring.

High performance flip-chip semiconductor device

MOSFET structure having improved source/drain junction performance

A circuit arrangement for interconnecting electronic components such as integrated circuit devices, chip packages and/or circuit boards includes signal, first fixed potential (e.g., power) and second fixed potential (e.g., ground) interconnects arranged into an interconnection layout pattern that offers greater flexibility, performance and cost effectiveness than conventional patterns. In some implementations, the interconnection layout pattern incorporates one or more tiles of interconnects, with each tile defining a plurality of interconnect positions arranged into at least three rows and at least four columns. For each tile, a signal interconnect is disposed at each of the three interconnect positions in each of the first and fourth columns, and one each of a signal interconnect, a first fixed potential interconnect and a second fixed potential interconnect are disposed in each of the second and third columns. In other implementations, the interconnection layout pattern arranges the interconnects into an array that defines interior and boundary interconnect positions, with each interconnect disposed at an interior interconnect position bordered on each side by another interconnect in the array, and with each signal interconnect disposed at an interior interconnect position in the array immediately adjacent to at least one first fixed potential interconnect and at least one second fixed potential interconnect.

Interconnect layout pattern for integrated circuit packages and the like

The present invention includes a micro-electromechanical system and voltage shifter, method of synchronizing an electronic system and a micromechanical system of a micro-electromechanical system. According to one aspect, the present invention provides a micro-electromechanical system voltage shifter including at least one node; a capacitor including plural opposing conductive plates; a micromechanical system configured to vary the capacitance of the capacitor; an electrical system configured to selectively couple the capacitor and the at least one node; and a mixer configured to output a product signal to synchronize the micromechanical system and the electrical system. Another aspect provides a method of synchronizing an electronic system and a micromechanical system of a micro-electromechanical system voltage shifter, the method including providing a capacitor and at least one node; varying the capacitance of the capacitor using a micromechanical system; selectively coupling the capacitor with the at least one node using an electrical system to one of charge the capacitor and provide sampling of the voltage of the capacitor; and synchronizing the electrical system and the micromechanical system.

Micro-electromechanical system and voltage shifter, method of

Disclosed is a redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device and a method for making the same. The redistribution layer includes a plurality of slot pads arranged along a periphery of the redistribution layer. The plurality of slot pads are formed from the patterned metallization layer. An array of bump pads are arranged in an inner portion of the redistribution layer such that the plurality of slot pads surround the array of bump pads, and the array of bump pads are formed from the patterned metallization layer. The redistribution layer further includes a plurality of traces that are formed from the patterned metallization layer and are configured to interconnect the plurality of slot pads to the array of bump pads. Each of the traces has a width that is selected to substantially equalize a resistance parameter associated with each of the plurality of traces. Additionally, each trace may include a bump pad area and possibly capacitance extending stubs that may be custom sized to substantially equalize a capacitance parameter associated with each of the plurality of traces.

Apparatus for equalizing signal parameters in flip chip redistribution

A circuit arrangement for a flip chip utilizes fixed potential shield traces between various signal traces in a redistribution layer to decrease coupling impedances and crosstalk within the layer. In particular, by orienting a fixed potential shield trace between a pair of signal traces and/or between a pair of differential trace pairs, capacitive coupling between the traces is greatly reduced, thereby permitting the signal traces to be routed closer to one another than would be possible if the shield trace was omitted. Often, minimum line width and spacing design rules may be met to ensure maximum circuit density for the redistribution layer and the associated device interconnections, and without concern for excessive adverse effects due to capacitive coupling between traces in the redistribution layer.

Flip chip circuit arrangement with redistribution layer that minimizes

The present invention is a micro-electromechanical voltage shifter. According to one embodiment, the voltage shifter of the present invention comprises a capacitor and micro-electromechanical means for changing a capacitance of the capacitor. The capacitor is initially charged and then electrically isolated. When the capacitance is altered, potential difference across the capacitor is shifted accordingly. In one embodiment of the present invention, the micro-electromechanical means includes a gear wheel driven by a micro-motor. The gear wheel preferably includes a plurality of teeth protruding along a circumference of the gear wheel. Further, the gear wheel is positioned next to the capacitor and configured to move the teeth into and out of a gap between the capacitor plates. As the teeth is preferably made of dielectric material, the voltage across the capacitor is changed as a tooth enters or leaves the gap. In another embodiment, the teeth may be made of a conducting material. The thickness of the teeth may also vary to provide a wide range of voltage levels.

Growing community of inventors

Santa Clara, CA, United States of America

Jayarama N Shenoy