Xilinx, Inc.

Jayaram Pvss

Ravinder Sharma

Robert Bellarmin Susai

Sebastian Turullols

Ramesh R Subramanian

Devanjan Maiti

Khang Kim Dao

Stephen P Rozum

Kyle Corbett

Lester S Sanders

Sudipto Chakraborty

Ch Vamshi Krishna

Kaustuv Manji

Siva Santosh Kumar Pyla

Manjunath Chepuri

Susheel Kumar Puthana

Michael Zapke

Naga Murali Narasimha Rao Medeme

Kaustuvmani Manji

Indlamuri Hemanth Kumar

Shravanthi Katam

Abhinaya Katta

Syed S Khader

Methods and systems to manage an environmental condition, such as power consumption and/or temperature, of an integrated circuit (IC) device by controlling a bandwidth of a packet-based communication interface of the IC device (e.g., a PCIe interface). Bandwidth may be controlled by controlling delay between packets or controlling delay of a handshake signal. Delay may be increased when the environmental condition reaches a first threshold. Delay may be reduced when the environmental condition falls to a second threshold. Bandwidth may be regulated with proportional-integral control provided by a firmware controller and/or hardware. Bandwidth may be separately controlled for upstream and downstream paths based on bandwidth utilization of the respective paths. Bandwidth control may utilize codes stored in selectable registers. The IC device may include a field programmable gate array (FPGA) and may be configured as an accelerator card.

Power and temperature driven bandwidth throttling using delay insertion

Examples herein describe a scalable tweak engine and prefetching tweak values. Regarding the scalable tweak engine, it can be designed to accommodate different bus widths of data. The scalable tweak engine described herein includes multiple tweak calculators that can be daisy chained together to output multiple tweak values every clock cycle. These tweak values can be sent to multiple encryption cores so that multiple data blocks can be encrypted in parallel. Regarding prefetching tweak values, previous encryption engines incur a delay as the tweak value (e.g., a metadata value) for a data block is calculated. In the embodiments herein, the encryption engine can include an independent metadata engine that determines the metadata value for a subsequent data block while the current data block is being encrypted.

Scalable tweak engines and prefetched tweak values for encyrption engines

Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

Flat shell for an accelerator card

N key generation circuits are arranged in a pipeline having N stages. Each key generation circuit is configured to generate a round key as a function of a respective input key and a respective round constant. Output signal lines that carry the round key from a key generation circuit in a stage of the pipeline, except the key generation circuit in a last stage of the pipeline, are coupled to the key generation circuit in a successive stage of the pipeline to provide the respective input key.

Distributed key expansion

An integrated circuit (IC) device includes a network device including a first network port, a second network port, and an internal endpoint port. The IC device further includes a first processing unit including an internal end station. The first processing unit is configured to communicate with the network device using the internal endpoint port. The IC device further includes a second processing unit including a bridge management layer. The second processing unit is configured to communicate with the network device using the internal endpoint port. In various embodiments, the first processing unit and the second processing unit are configured to communicate with each other using a first internal channel.

Systems and methods for discovery and configuration of a network device

A circuit for memory access includes a memory access control circuit. The memory access controller is coupled to a memory and configured to perform data transfers to retrieve data from the memory. The memory access control circuit includes a timing control circuit and a transfer control circuit. The timing control circuit is configured to determine first timing information based on a timing requirement for transmitting a first data stream to a first network; and determine a first fetch time for retrieving the first data stream from the memory based on the first timing information. The transfer control circuit is configured to retrieve the first data stream from the memory based on the first fetch time.

Method and apparatus for direct memory access transfers

An apparatus can include an interface circuit configured to receive an operating parameter and a control circuit coupled to the interface circuit and configured to store the operating parameter. The apparatus also can include a clock error detection circuit coupled to the control circuit. The clock error detection circuit can be configured to detect a clock error condition on a clock signal based upon the operating parameter and, responsive to detecting the clock error condition, generate a signal indicating an occurrence of the clock error condition.

Programmable clock monitor

The disclosed approaches compile a hierarchical representation of a circuit design into a flattened netlist and store the flattened netlist a memory circuit. The circuit design instantiates a plurality of memory blocks of a target device and specifies logic circuits that access the plurality of memory blocks, respectively. The flattened netlist is modified by determining a subset of the plurality of memory blocks. The quantity of memory reserved in each memory block of the subset is less than a capacity of said each memory block. One memory block is instantiated, for a pair of the memory blocks of the subset, in place of each memory block of the pair in the flattened netlist in the memory circuit. A portion of the flattened netlist that specifies the logic circuits that access each memory block of the pair is modified to access the one memory block instead of each memory block of the pair.

Memory utilization in a circuit design

Growing community of inventors

Hyderabad Telangana, India

Jayaram Pvss