Qualcomm Incorporated

Nxp B.v.

Jayanth Mandayam

Marcello Vincenzo Lioy

Jeffrey Alan Dyck

Ron Keidar

Mark Leonard Buer

Roy Franklin Quick, Jr

Sudeep Ravi Kottilingal

Jeff Dyck

Sudeep Kittilingal

A processor for processing data from a buffer memory, implemented in hardware, may allow writing of output data, processed based on input data from at least one secure location associated with a secure address range of the buffer memory, to one or more secure locations associated with the secure address range. Further, the processor may block writing of output data, processed based on input data from at least one secure location associated with the secure address range, to one or more insecure locations associated with an insecure address range of the buffer memory.

Apparatus and method for hardware-based secure data processing using buffer memory address range rules

A device may include countermeasure circuitry that provides a countermeasure check that protects device logic. The device may also include enforcement circuitry that non-deterministically enforces the countermeasure check on the device logic so that the device logic is not always protected by a countermeasure action within the countermeasure check. The device may non-deterministically enforce the countermeasure check according to an enforcement rate, and the device may adjust the enforcement rate depending on a priority of the device logic or device logic portion protected by a particular countermeasure check.

Randomizing countermeasures for fault attacks

A processor is utilized for processing data from a buffer memory. The processor, implemented in hardware, may allow writing of output data, processed based on input data from at least one secure location associate with a secure address range of the buffer memory, to one or more secure locations associated with the secure address range. Further, the processor may block writing of output data, processed based on input data from at least one secure location associated with the secure address range, to one or more insecure locations associated with an insecure address range of the buffer memory.

This disclosure describes a key update scheme for use in a mobile IP network. The update scheme may be implemented to facilitate key updates between a mobile device and a server computer that authenticates the mobile device. The techniques described herein can facilitate key updates in a manner that accounts for potential message loss during the update routine, mobile device failure during the update routine, or other problems typically encountered in a mobile network settings. In this manner, the techniques can provide a robust scheme for key updates and may improve network security.

Key updates in a mobile wireless system

Methods and apparatus are presented herein for allowing a keyless access terminal (AT) to access a packet serving data node (PSDN) over a service network stream without deactivating the authentication functions of the authentication network stream.

Method and apparatus for supporting access network (AN) authentication

A method and system for link latency determination in a Mobile IP network determine an unloaded network delay; set a current estimated delay; initiate a current round trip estimation process; and set a retry timer. If the retry timer expires before the process completes, the method and system update the predetermined backoff period and repeat the preceding two steps. After re-registration, the method and system reset the current estimated delay time. The link latency determination optimizes the re-registration process between a mobile device and an agent device, thereby enhancing mobile device communications, minimizing network loading, and optimizing network traffic levels.

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San Diego, CA, United States of America

Jayanth Mandayam