Freescale Semiconductor,inc.

Nxp Usa, Inc.

Freescale Semiconductors Inc.

Jayanta Bhadra

Magdy Samuel Abadir

Xiushan Feng

Wen Chen

Mrinal Bose

Monica Claudia Farkash

Himyanshu Anand

Hillel Miller

Lawrence Loren Case

Xiao Sun

Ashish Goel

Edward L Swarthout

Jing Zeng

Vivekananda Vedula

Ping Gao

Timothy David McDougall

Kenneth G Davis

Yaniv Fais

Sharon Goldschlager

Yinfang Lin

Amit Hermony

Prashant U Naphade

Sandip Ray

Kuo-Kai Hsieh

Scott R Little

Pankaj Sharma

Ross L Patterson

Robert S Slater

M Alper Sen

Ekaterina A Trofimova

A security system for vetting run-time operation of device hardware. A model stores vetted states based on device hardware security signals, a severity level value and at least one vetted next state. The vetting system compares each state of the device hardware with the vetted next states of a current state, and provides an indication and a severity level when the real next state does not match a vetted next state. In response to the indication, the synchronization system performs synchronization by comparing each subsequent real next state of the device hardware with the vetted states until initial synchronization occurs when any subsequent real next state matches a vetted state. The learning system receives feedback from the device hardware in response to the indication, and when indicated by the feedback, updates the model in accordance with the feedback.

Run-time security protection system and method

A method, system, and architecture () for adaptively field testing for hardware faults on an integrated circuit device includes a central quality assurance server () which receives specified hardware metric data () monitored at an integrated circuit device () in the field, identifies prioritized built-in self-test (BIST) fault detection tests () based on the specified hardware metric data, securely downloads the prioritized BIST fault detection tests () to the integrated circuit device for execution to identify a first hardware fault at the integrated circuit device, and then receives diagnosis information () identifying the first hardware fault from the integrated circuit device which is used to update the prioritized BIST fault detection tests.

System architecture method and apparatus for adaptive hardware fault detection with hardware metrics subsystem

Self-configured, power-aware circuitry configured to enhance power efficiency within integrated circuitry by self-calibrating the power consumption utilized within the integrated circuitry according to the requirements of an application program running within the integrated circuitry. The power consumption is self-calibrated within the integrated circuitry on a per application-based manner so that the integrated circuitry can be implemented with a plurality of various generalized functionalities, each of which may or may not be utilized while a specific application program is running within the integrated circuitry. Power consumption within the integrated circuitry is reduced by independently and dynamically controlling multiple power sections delineated within the integrated circuitry.

Autonomous hardware for application power usage optimization

A runtime classifier hardware circuit is incorporated into an electronic device for implementing hardware security by storing a support vector model in memory which is derived from pre-silicon verification data to define secure behavior for a first circuit on the electronic device; monitoring input and/or output signals associated with the first circuit using the runtime classifier hardware circuit which compares the input and/or output signals to the support vector model to detect an outlier input signal and/or outlier output signal for the first circuit; and blocking the outlier input and/or output signal from being input to or output from the first circuit.

Model-based runtime detection of insecure behavior for system on chip with security requirements

Transactions in a multi-component system have corresponding local identifiers uniquely identifying the transaction among transactions within a particular functional block of the device under test. For each transaction, it is determined whether the transaction is a new request, a handshake request corresponding to a previously generated request, or a response. In response to determining that a transaction of the plurality of transactions is a new request, a global identifier is assigned to the new request which uniquely identifies the new request among new requests of all functional blocks of the device under test. A global entry corresponding to the new request is stored that includes the global identifier of the new request, an indicator of a functional block of the device under test which generated the new request, and a local identifier uniquely identifying the new request within the first functional block.

Systems and methods for analyzing transactions in a computer system

An approach is provided in which an equivalence class generator selects a configurable module that includes control points and configuration parameters. The configuration parameters define a parameter state space of the configurable module. The equivalence class generator utilizes the control points to generate equivalence classes, which include class representatives that indicate values for the configuration parameters. Next, one of the class representatives are selected and verified from each of the equivalence classes. In turn, the verification of the class representatives verifies the parameter state space of the configurable module.

Equivalence classes over parameter state space

An approach is provided in which a power design verification system retrieves a power intent data corresponding to a power design, which identifies the power design's power modes and power mode transition conditions. The power design verification system selects one of the power mode transition conditions, which identifies input signals that invoke a transition from a first power mode to a second power mode. In turn, the power design verification system generates simulation stimuli based upon the identified input signals and simulates the power design utilizing the generated simulation stimuli accordingly.

Verification of design derived from power intent

An approach is provided in which a computing system retrieves a design description that corresponds to an electronic circuit design. The computing system selects an assertion corresponding to the electronic circuit design, which includes one or more assertion signal identifiers corresponding to one or more description signal points included in the design description. Next, the computing system creates a partitioned region from the design description based upon the description signal points. The computing system compiles and verifies the partitioned region that, in turn, verifies the electronic circuit design.

Assertion-based design partitioning

An approach is provided in which a formal verification tool sends a condition signal to a first circuit instance and to a second circuit instance, which are both instances of an electric circuit design. The formal verification tool selects a common input port and sends a first input value to the common input port of the first circuit instance and sends a second input value, which is different than the first input value, to the common input port of the second circuit instance. In turn, the first circuit instance generates a first output value and the second circuit instance generates a second instance value, which are utilized to verify dependencies between the electronic circuit's input ports and output ports.

Automatic verification of dependency

A test system collects passing event data and failing event data, and merges the collected data into passing subsequences and failing subsequences, respectively. The test system identifies an overlap area between the passing subsequence and the failing subsequence in regards to time slices and tracepoint slices, and creates passing transactions and failing transactions using the event data corresponding to the overlap area. Next, the test system detects a timing discrepancy between the first passing transaction relative to the second passing transaction compared with the first failing transaction relative to the second failing transaction. The test system then reports the detected timing discrepancy, which allows a test engineer to perturb the test program in order to more frequently catch intermittent failures caused by asynchronous timing conditions.

Trace reconstruction for silicon validation of asynchronous systems-on-chip

A method, data processing system, and computer program product are provided for performing time-based symbolic simulation. A delay-aware representation of a circuit is created that includes a plurality of circuit nodes. The data-aware representation is simulated. In particular, the simulator simulates transitions from a first set of circuit nodes to a second set of circuit nodes selected from the plurality of circuit nodes, the simulating based on executing a first set of simulation events. A second set of simulation events is then generated in response to executing the first set of simulation events. During the simulation, a time is computed for each of the transitions. An an event scheduling diagram is constructed during simulation. The event scheduling diagram depicts the transitions and the times of the transitions.

System and method for circuit symbolic timing analysis of circuit designs

An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set of transactors sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.

Stream based stimulus definition and delivery via interworking

A method and device for determining memory element and intermediate point correspondences between design models is disclosed. The method includes developing graph representations of two circuit design models of an electronic device. The circuit design models each include input and output nodes corresponding to input and output nodes of the electronic device. The circuit design models also include memory and intermediate nodes corresponding to memory elements and intermediate points, respectively of the electronic device. An intermediate point represents a point between memory elements of the electronic device, and so can represent logic gates or other modules of the device. Memory elements and intermediate points can be referred to collectively as circuit elements. Nodes in the graph representation represent inputs, outputs, memory elements or intermediate points in the design models. A correspondence between the circuit elements in circuit design models is determined based on the graph representations.

Model correspondence method and device

A method and system automatically generates a bit-cell correspondence between a first memory model and a second memory model of a memory. The method includes receiving data from the first and the second memory model, obtaining true-inverted fan-in cones for words in the memory models to obtain correspondence between sets of words in the two models, writing word binary sequences into the words to obtain a set of bit-cell correspondences, and using inherent structural information in memory designs to generalize bit-cell correspondence obtained on bit-cells of a pair of corresponding words to obtain bit-cell correspondence information for all the bit-cells in the memory models. Correspondence is detected if one of the bit-cell binary sequences written into a bit-cell in the first memory model is equal to or an invert of another of the bit-cell binary sequences written into a bit-cell in the second memory model.

Design analysis tool and method for deriving correspondence between storage elements of two memory models

A design analysis tool performs path extraction translation and false path identification functions. The design analysis tool is utilized with a conventional automated test pattern generator and timing analysis tools. By checking for four specific criteria, a fast and efficient way to detect whether a circuit path is false or active is accomplished. A final value condition is checked and, if that test is met, a side value propagation condition is checked. Assuming both tests result in the path still being active, the test is terminated. If the side value propagation conditions are not satisfied, then an initial value condition and a slower path condition is checked. The checks are made to determine whether or not conditions exist in the path that makes the path false. The information may be obtained quickly from the timing analysis information and the result of the ATPG tool.

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Austin, TX, United States of America

Jayanta Bhadra