Synopsys, Inc.

Jayant Nagda

Parijat Biswas

Alexandru Seibulescu

Raghurama Krishna Srigiriraju

In a method for increasing coverage convergence during verification of a design for an integrated circuit, multiple simulation runs can be performed. Symbolic variables and symbolic expressions can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Exemplary hardware code can include the hardware description language (HDL) code and/or the hardware verification language (HVL) code. Symbolic properties, which are derived from propagating the symbolic variables and symbolic expressions through the design and the test bench during the multiple simulation runs, can be collected. Coverage information from the multiple simulation runs can be analyzed to identify coverage points to be targeted. At this point, for each identified coverage point, the constraints resulting from the collected symbolic properties can be solved to generate directed stimuli for the design. These directed stimuli can increase the coverage convergence.

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Fremont, CA, United States of America

Jayant Nagda