Nvidia Corporation

Jayant B Kolhe

Ian Buck

Nicholas P Wilt

Julius Vanderspek

Bastiaan Aarts

Vinod Grover

Robert Steven Glanville

Boris Beylin

Michael Murphy

Bastiaan Joannes Matheus Aarts

Douglas Saylor

Michael G Ludwig

Henry Packard Moreton

John R Nickolls

Lars Nyland

Michael T Bunnell

Richard Craig Johnson

Geoffrey C Berry

John Bryan Pormann

One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU.

Execution of retargetted graphics processor accelerated code by a general purpose processor

Retargetting an application program for execution by a general purpose processor

One embodiment of the present invention sets forth a technique for representing and managing a multi-architecture co-processor application program. Source code for co-processor functions is compiled in two stages. The first stage incorporates a majority of the computationally intensive processing steps associated with co-processor code compilation. The first stage generates virtual assembly code from the source code. The second stage generates co-processor machine code from the virtual assembly. Both the virtual assembly and co-processor machine code may be included within the co-processor enabled application program. A co-processor driver uses a description of the currently available co-processor to select between virtual assembly and co-processor machine code. If the virtual assembly code is selected, then the co-processor driver compiles the virtual assembly into machine code for the current co-processor.

System and method for representing and managing a multi-architecure co-processor application program

A virtual architecture and instruction set support explicit parallel-thread computing. The virtual architecture defines a virtual processor that supports concurrent execution of multiple virtual threads with multiple levels of data sharing and coordination (e.g., synchronization) between different virtual threads, as well as a virtual execution driver that controls the virtual processor. A virtual instruction set architecture for the virtual processor is used to define behavior of a virtual thread and includes instructions related to parallel thread behavior, e.g., data sharing and synchronization. Using the virtual platform, programmers can develop application programs in which virtual threads execute concurrently to process data; virtual translators and drivers adapt the application code to particular hardware on which it is to execute, transparently to the programmer.

Virtual architecture and instruction set for parallel thread computing

System and method for representing and managing a multi-architecture co-processor application program

A method and apparatus for optimizing register allocation during scheduling and execution of program code in a hardware environment. The program code can be compiled to optimize execution given predetermined hardware constraints. The hardware constraints can include the number of register read and write operations that can be performed in a given processor pass. The optimizer can initially schedule the program using virtual registers and a goal of minimizing the amount of active registers at any time. The optimizer reschedules the program to assign the virtual registers to actual physical registers in a manner that minimizes the number of processor passes used to execute the program.

Method and apparatus for register allocation in presence of hardware constraints

A list scheduler in a compiler can select from a plurality of alternative instruction sequences for one or more computation performed within an application. A scheduler can initially identify and track one or more computations for which multiple alternative instruction sequences exist. An available instruction list can be populated with the alternative instruction sequences. The list scheduler can access the available instruction list during scheduling of the application. The list scheduler can perform a cost analysis while scheduling the instructions by performing a look ahead. The list scheduler may select alternate instruction sequences for similar computations occurring in different portions of the application based on the cost benefit analysis.

Dynamic instruction sequence selection during scheduling

Growing community of inventors

Milpitas, CA, United States of America

Jayant B Kolhe