Cypress Semiconductor Corporation

Infineon Technologies LLC

Jayant Ashokkumar

David W Still

Joseph S Tandingan

James D Allan

Jesse J Siman

Iulian Constantin Gradinariu

Vijay Raghavan

Fan Chu

Shan Sun

Judith E Allen

Bogdan Samson

David Gordon Wright

Venkatraman Prabhakar

Alan D DeVilbiss

Donald J Verhaeghe

Swatilekha Saha

John Roger Gill

Qidao Li

Srikanth Reddy Tiyyagura

Mohandas Sivadasan

Abhisek Dey

Gregory W Pauls

In accordance with an embodiment, a circuit includes a plurality of comparators disposed on an integrated circuit, the plurality of comparators having inputs coupled to a monitored power supply line; and a voting circuit having inputs coupled to outputs of the plurality of comparators. An output of the voting circuit is configured to provide a signal indicative of a brown out condition of a power source coupled to the monitored power supply line.

Glitch free brown out detector

A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN) and controlled by a first wordline (WL), a second transistor coupled between a reference line and the SN and controlled by a second wordline (WL), and a ferro-capacitor coupled between the SN and a plateline. The device further includes a sense-amplifier coupled to the bit-line and reference line, and a processing-element configured to issue control signals to WL, WL, the plateline and the sense-amplifier. The cell is configured and operated to generate a bit-level reference in which a first voltage pulse is applied to the plateline during a read cycle for the data pulse and a second voltage pulse serves as a reference pulse and as a clear pulse.

2T1C ferro-electric random access memory cell

Systems, methods, and devices for providing power to low energy circuits include inrush circuits. Devices include a regulator that includes at least one driver device configured to generate a first current associated with a load comprising a low energy integrated circuit. Devices also include a bias generator configured to generate a second current to charge a load capacitor coupled with a power terminal of the low energy integrated circuit. Devices further include an enable circuit configured to enable the bias generator and disable the regulator responsive to a load voltage being below a threshold voltage, and further configured to enable the regulator to generate the first current and disable the bias generator responsive to the load voltage being above the threshold voltage.

Low inrush circuit for power up and deep power down exit

A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of operation thereof

A circuit includes a biasing circuit that includes a diode stack coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a transistor, a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the diode stack in response to a transition of the ISO signal between a first voltage and a second voltage. The biasing circuit also is configured to output a signal to a level shifter to hold an output of the level shifter in a known state for a specified amount of time after power-up of the circuit for proper operation of the level shifter.

Biasing circuit for level shifter with isolation

A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM element, the second transistor is coupled to a second node of the NVM element and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement. The volatile portion includes cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage (VPWR) and the first output node, and the second FET coupled between VPWR and the second output node. A gate of the first FET is coupled to the second output node, and a gate of the second FET is coupled to the first output node.

Split voltage non-volatile latch cell

Multi-bit non-volatile random access memory cells are disclosed. A multi-bit non-volatile random access memory cell may include a volatile storage element and a non-volatile storage circuit. The non-volatile storage circuit may include at least one first pass transistor connected to a data true (DT) node of the volatile storage element and at least one second pass transistor connected to a data complement (DC) node of the volatile storage element. The non-volatile storage circuit may also include multiple non-volatile storage elements. Each non-volatile storage element may be configured to be selectively connectable to the DT node of the volatile storage element via the at least one first pass transistor and selectively connectable to the DC node of the volatile storage element via the at least one second pass transistor, allowing the multi-bit non-volatile random access memory cell to store/recall more than one databit per cell.

Multi-bit non-volatile random-access memory cells

A memory device and array which includes a static random access memory (SRAM) circuit coupled to a non-volatile circuit, such as a ferroelectric-RAM (F-RAM) circuit, in which the F-RAM circuit stores a bit of data from the SRAM circuit during power-out periods, the F-RAM circuit is further coupled to bit-line(s) to output the bit of data stored in the F-RAM circuit when operation power is restored.

Non-volatile static RAM and method of operation thereof

A circuit includes a biasing circuit that includes a load circuit coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the load circuit in response to a transition of the ISO signal between a high voltage and a low voltage. The biasing circuit also includes circuitry to generate an isolation delayed (ISO_DEL) signal. The ISO_DEL signal has a high voltage in response to the biasing signal being within a first threshold level and the ISO_DEL signal has a low voltage in response to the biasing signal being within a second threshold level. The biasing circuit outputs the ISO_DEL signal.

A verification circuit for a capacitor power supply measures at least two voltages across the terminals of the capacitor at two points in time, the two points in time defining a time interval dT. A change in voltage dV over the time interval dT is determined. An operation powered by the capacitor is initiated, or not, by deriving from the time interval dT and/or the voltage change dV, a total required time or a total required voltage for completing the operation, and comparing the total required time or total required voltage to a pre-determined necessary total time or predetermined necessary total voltage, respectively (a 'time interval test').

Capacitor power source tamper protection and reliability test

The state of a volatile memory cell is set by grounding a power supply to the volatile memory cell and driving a first bit line to the volatile memory cell to a first defined state. The first defined state of the first bit line is controllable independently of a defined state of a second bit line to the volatile memory cell. A word line of the volatile memory cell is driven to a word line state, and the power supply to the volatile memory cell is ungrounded.

Method and apparatus to implement a reset function in a non-volatile static random access memory

A system and method for programming and erasing a semiconductor memory is disclosed. More particularly, the present invention uses the bit lines of a volatile memory portion of semiconductor memory so as to program and erase the non-volatile portion of the semiconductor memory.

Method and apparatus to program and erase a non-volatile static random access memory from the bit lines

A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.

Growing community of inventors

Colorado Springs, CO, United States of America

Jayant Ashokkumar