Intel Corporation

Jayakrishna P S

Altug Koker

Abhishek R Appu

Joydeep Ray

Elmoustapha Ould-Ahmed-Vall

Varghese George

Mike MacPherson

Pattabhiraman K

Subramaniam M Maiyuran

Vasanth Ranganathan

Aravindh V Anantaraman

Valentin Andrei

Prasoonkumar Surti

Debendra Das Sharma

Ravishankar Iyer

Eric C Samson

Ben J Ashbaugh

Nicolas C Galoppo Von Borries

Scott R Janus

Selvakumar Panneer

Lakshminarayanan Striramassarma

Josh B Mastronarde

Sridhar Muthrasanallur

Nilesh K Jain

Eric R Wehage

Saurabh Tangri

Sudhakar Kamma

Sean Coleman

K Pattabhiraman

Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

Cache structure and utilization

Methods and apparatus relating to techniques for data compression. In an example, an apparatus comprises a processor receive a data compression instruction for a memory segment; and in response to the data compression instruction, compress a sequence of identical memory values in response to a determination that the sequence of identical memory values has a length which exceeds a threshold. Other embodiments are also disclosed and claimed.

Compression techniques

Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

Graphics processor operation scheduling for deterministic latency

Methods and systems may provide for receiving a request to perform an atomic operation and adding the atomic operation to an execution pipeline of an arithmetic logic unit (ALU) for one or more pending atomic operations if the one or more pending atomic operations are associated with a memory location identified in the request. Additionally, at least a portion of the execution pipeline may bypass the memory location. In one example, adding the atomic operation to the execution pipeline includes populating a linked list with a modification associated with the atomic operation, wherein the linked list is dedicated to the memory location.

System and method of using an atomic data buffer to bypass a memory location

A method and system of error recovery of a device attached to a platform without requiring a system reset. In one embodiment of the invention, a platform detects an error(s) of an attached device and shuts down the communication link with the attached device. The platform corrects the error(s) and automatically re-trains the communication link with the attached device. In this way, no reset of the platform is required to correct the detected error(s) in one embodiment of the invention.

Method and system of live error recovery

Growing community of inventors

Bengaluru, India

Jayakrishna P S