Hewlett-packard Development Company, L.p.

Jay Tsao

Theodore Carter Briggs

Craig William Warner

Chris Michael Brueggen

There is disclosed systems and methods for testing a memory where at least one bit field at certain address locations cannot be directly accessed. In one embodiment, random bits are populated into a data field at one of the certain address locations, and at least some of the random data bits that are copied into non-directly accessible data field. The bits which were copied from the data field are replaced with bits resulting from X/ORing the copied data bits with bits read from the non-directly accessible field, and all the data field bits as the address locations are checked for mismatched data bits.

System and method for testing memory at full bandwidth

Reading and writing data from a plurality of memory devices. A code word having a plurality of bits is partitioned into nibbles. Adjacent nibbles are stored on a common physical medium. The failure of the common physical medium results in errors in adjacent nibbles of a reconstructed code word.

Partitioning data for error correction

Systems and methods are provided for detecting and correcting bit errors in data structures. A data block and/or data structure is partitioned into adjacent bit pair domains, such that a single adjacent bit pair from each memory device is assigned to a given adjacent bit pair domain. The bits in the adjacent bit pair domain are processed by an error correction unit sequentially or in parallel, and then recombined to be written into memory or transmitted to a requestor.

Systems and methods of partitioning data to facilitate error correction

Systems and methods are provided for detecting and correcting bit errors in data structures. A data block and/or data structure is partitioned into adjacent bit pair domains, such that a single adjacent bit pair from each memory device is assigned to a given adjacent bit pair domain. The adjacent bit pair domain data is transmitted over a bus having a plurality of data paths, such that data bits associated with a given memory device are transmitted over a same data path.

Systems and methods of routing data to facilitate error correction

A system and method for data communication in a multi-controller environment is disclosed. The system and method utilize a sequence number protocol to filter duplicate packets, adapt to transient errors, and to reroute data packets to avoid hardware malfunctions. The system and method further employ a transaction database to track packet communication in accordance with the sequence numbers. Moreover, the system and method may be implemented in hardware or software to provide a transparent transport layer to higher level hardware layers. The system and method utilize sequence number domains and a bridging protocol to reduce requirements associated with maintaining sequence number threads.

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Plano, TX, United States of America

Jay Tsao