Xilinx, Inc.

Other

Jay T Young

Ian L McEwen

Jeffrey V Lindholm

Sridhar Krishnamurthy

William R Troxel

Jeffrey M Mason

W Story Leavesley, Iii

Walter A Manaker, Jr

Carl M Stern

Eric Ford Dellinger

David Wayne Bennett

Steven P Young

Brian C Gaide

Eric F Dellinger

Andrew W Lai

Randy J Simmons

Reto Stamm

Salim Abid

Vincent L Tong

Chirag Ravishankar

Teymour M Mansour

Davis Moore

A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.

Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvements

A method of selecting routing resources in a multi-chip integrated circuit device is described. The method comprises placing a design on the multi-chip integrated circuit device; estimating a number of vias required to enable connections between chips of the multi-chip integrated circuit device that is placed with a portion of the design; identifying an area of a chip having a number of vias that is greater than a maximum number of vias for the area of the chip; selecting a partition window defining resources in the chip that is placed with the portion of the design, where in the partition window is selected to allow the number of vias to meet a maximum requirement of vias for the partition window; and re-placing the portion of the design within the partition window so that the number of vias in the area of the chip is within the maximum number of vias for the area.

Method of selecting routing resources in a multi-chip integrated circuit device

Methods of prioritizing untested routing resources in programmable logic devices (PLDs) to generate test suites that include a minimal number of test designs. The untested routing resources are prioritized (e.g., placed into an ordered list) based on a number of untested input or output terminals for each untested resource. The number of untested input or output terminals (whichever is larger) for each routing resource determines the minimum number of additional test designs in which the routing resource must be included. The resulting prioritization can be utilized by a router, for example, to first include in test designs those routing resources that must be included in the largest remaining number of test designs. The described prioritization methods can also be used to select one of two or more test designs that should be included in the overall test suite. In each case, the overall number of test designs is reduced.

Methods of prioritizing routing resources to generate and evaluate test designs in programmable logic devices

A method of processing a logical netlist for implementing a circuit design within a programmable integrated circuit includes identifying a dynamically reconfigurable module (DRM) comprising a port from the logical netlist. The DRM defines a dynamically reconfigurable region of the integrated circuit that communicates with a module that is not dynamically reconfigurable via the port. First circuitry of the DRM and circuitry external to the DRM are implemented. The first circuitry connects to the circuitry external to the DRM via the port. The circuitry external to the DRM is within the module that is not dynamically reconfigurable. The method further includes locking routing resources connecting the circuitry external to the DRM to a location associated with a boundary of the DRM for the port; and implementing second circuitry of the DRM by reusing the locked routing resources. The second circuitry is routed to connect to the location associated with the boundary of the DRM for the port.

Generating a module interface for partial reconfiguration design flows

A method of processing a logical netlist for implementing a circuit design within a programmable logic device includes identifying a dynamically reconfigurable module (DRM) including at least one port from the logical netlist and determining whether the port connects with function logic for a function of the DRM. If the port connects with function logic, logic is inferred that connects the function logic with logic that is external to the DRM. If the port does not connect with function logic, logic is inferred that connects the port of the DRM with logic that is external to the DRM according to an attribute associated with the port. The logical netlist is updated to specify the inferred logic.

Method and apparatus for providing secure intellectual property (IP) cores for a programmable logic device (PLD) are described. An aspect of the invention relates to a method of securely distributing an IP core for PLDs. A circuit design is generated for the IP core, the circuit design being re-locatable in a programmable fabric for PLDs. The circuit design is encoded to produce at least one partial configuration bitstream. Implementation data is generated for utilizing the IP core as a reconfigurable module in top-level circuit designs. The at least one partial configuration bitstream and the implementation data are delivered to users of the PLDs.

Method and apparatus for providing secure intellectual property cores for a programmable logic device

Method and apparatus for generating an area constraint for a module in a programmable logic device (PLD) is described. In an example, first logic resources are selected in a floorplan of the PLD for implementing a first module of a circuit design. A routing resource area constraint is defined that reserves first routing resources associated with the first logic resources and second routing resources associated with second logic resources. The second routing resources are required for use of the first logic resources. A logic resource area constraint is defined that reserves the first logic resources and excludes the second logic resources. The logic resource constraint area for the module may be non-rectangular or include multiple disjoint regions.

Method and apparatus for generating an area constraint for a module in a programmable logic device

Method, apparatus, and computer readable medium for modular circuit design for a programmable logic device (PLD) is described. In one example, a circuit design is captured. The circuit design includes a plurality of modules and one or more logic interface macros positioned on a floorplan. Each of the plurality of modules is one of a static module or a reconfigurable module. The one or more logic interface macros include programmable logic of the PLD and are positioned at one or more boundaries between one or more pairs of the plurality of modules. Each of the plurality of modules is implemented using information generated from the capturing step. The modules are assembled using the information generated from the capturing step and implementing step. Routing for a static module can cross a defined implementation area for a reconfigurable module, and a static module can be placed anywhere outside of reconfigurable module areas.

Method and apparatus for modular circuit design for a programmable logic device

A method for generating a design for an FPGA provides for partial reconfiguration by allowing relocation of the same single bitstream within different areas of the FPGA, reducing overall design time and PROM storage space needed for the design. The design rules for the method include a requirement that the same frames oriented in the same relative location be available in dynamic areas where a bit stream will be located. Further, the rules require the same relative communication interfaces be available between the dynamic areas and static areas when the bit stream is relocated. Additionally the design rules require global resources, such as clock resources used by the static areas remain the same when the bit stream is relocated.

Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements

The present invention includes an apparatus and method to optimize a set of test designs to obtain complete coverage while reducing bit stream size for programmable fabric. Test designs are selected that do not result in lost coverage. The method selects a set of test designs, removes the set of test designs, and then determines if coverage is lost. If coverage is lost, the method creates a new set of test designs to test the lost coverage. If the new set of test designs is smaller than the removed set, the new set of test designs is added to the test design suite; otherwise the removed test designs are added back to the test design suite. The decision to add the new test designs or removed test designs is based on a number of criteria including evaluating the number of uniquely tested resources in each test design.

Method and apparatus for reducing the number of test designs for device testing

A method of testing a programmable logic device (PLD) can include distinguishing between stages within the design that uniquely test a routing resource and stages that do not. The method also can include un-routing at least a portion of the design corresponding to one or more of the stages that do not uniquely test a routing resource. The stage(s) can be excluded from the design. The portion of the design that was un-routed can be re-routed by passing those stages that do not uniquely test a routing resource.

Reducing design execution run time bit stream size for device testing

Methods of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) compression technique to the resulting configuration bitstream. The methods apply placement patterns and/or routing templates to encourage the inclusion of numbers of duplicated routing paths in the routed design. The duplicated routing paths result in duplicated configuration data. Thus, a configuration bitstream implementing the routed design in the PLD includes numbers of duplicated configuration data frames, and is well-suited to benefit from MFW compression techniques.

Methods of routing programmable logic devices to minimize programming time

A method of routing a design on a programmable logic device (PLD) includes generating a database that identifies the correspondence between routing resources of the PLD and programming frames of the PLD. A first set of programming frames required to implement the logic of the design is identified, and the cost associated with using the first set of programming frames is eliminated. A second set of programming frames that are not used to implement the logic of the design is also identified, and the cost associated with using the second set of programming frames is maximized. Interconnect networks of the design are then routed, taking into account the costing of the programming frames. When a programming frame from the second set is used, the cost associated with using this programming frame is eliminated. This method minimizes used programming frames and maximizes unused programming frames, thus reducing PLD configuration time.

Routing with frame awareness to minimize device programming time and test cost

Methods of directly targeting specified routing resources in a PLD, e.g., routing resources that need to be tested. Test designs are produced that implement observable nets using the targeted routing resources. A PLD router is used to route from a target routing resource backwards through the routing fabric of the PLD to the source of an observable net. The net is identified based on the source, and loads of the net are identified as router load targets. The router is then used to route from the target routing resource forwards to one of the loads on the net. This process can be repeated for a list of target routing resources to provide a test design that tests as many of the targeted routing resources as possible. Additional test designs can be created to test remaining target routing resources. In other embodiments, the router routes first forwards, then backwards.

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Louisville, CO, United States of America

Jay T Young