Texas Instruments Corporation

Jay Sung Chun

Thomas Dyer Bonifield

Jeffrey Alan West

Elizabeth Costner Stewart

Zhiyi Yu

Joseph Andre Gallegos

Byron Lovell Williams

An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.

Integrated capacitor with sidewall having reduced roughness

Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.

Method of fabricating a thick oxide feature on a semiconductor wafer

A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.

In accordance with the invention, there are methods of controlling the sidewall angle of a polysilicon gate from batch to batch while maintaining current bottom critical dimension control performance. The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate, developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher, and predicting a sidewall angle using the statistical model for a given polydensity, a given polythickness, and a given etcher. The method can also include comparing the predicted sidewall angle with a target sidewall angle and determining an optimized RF bias power and optimized etch time of one or more etch steps during the formation of the gate using the correlation to match the target sidewall angle.

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Plano, TX, United States of America

Jay Sung Chun