Chipx Incorporated

Lsi Logic Gorporation

Jay Sherman Hidy

William H Gascoyne

Elie H Massabki

An in-circuit design and verification device, system and method are disclosed for cooperatively designing and verifying application-specific integrated circuit device prior to fabrication by emulating logical and specialized functions. By emulating specialized circuits of the ASIC, an in-circuit design and verification-device can advantageously detect errors that are not generally detectable by conventional techniques for verifying ASIC designs. In one embodiment, an in-circuit design and verification system includes programmable logic configured to emulate on-chip logic of an ASIC as well as a specialized function circuit configured to emulate a specialized function that the programmable logic cannot emulate. The in-circuit design and verification system also includes an emulation interface configured to exchange signals between the configured programmable logic and the specialized function circuit during in-circuit design and verification. The configured programmable logic and the specialized function circuit thus cooperate to emulate the ASIC.

In-circuit device, system and method to parallelize design and verification of application-specific integrated circuits ('ASICs') having embedded specialized function circuits

A method for providing a nonfunctional circuit design for evaluation in accordance with a static timing analysis is provided herein. The method initially generates a netlist, and then creates a standard delay format (SDF) file from the netlist. The standard delay format file contains occurrence names and delays associated with all elements of the design. The method subsequently selects elements of the design, alters the functionality of each selected element, and alters the standard delay format file entries corresponding to each selected element. The functional alteration of selected elements comprises altering an AND gate to be an OR gate, altering a NAND gate to be a NOR gate, altering an OR gate to be an AND gate, altering a NOR gate to be a NAND gate, altering an XOR to be an XNOR, and/or altering an XNOR to be an XOR in a predetermined manner. The method may accomplish random selection using a random number generator, or alternatively by visually selecting various design elements and altering the functionality of the gate as described. An alternative embodiment is disclosed wherein all elements having similar timing characteristics and different functionality are given identical functionality, such as all AND gates are changed to OR gates, so that all AND and OR gates have OR functionality.

Growing community of inventors

Saratoga, CA, United States of America

Jay Sherman Hidy