Cisco Technology, Inc.

Intel Corporation

Cisco Systems Inc.

Jay Sethuram

Richard Joseph Weber

Chandra Shekhar Joshi

Srinivasa Rao Malladi

Rajiv Dattatraya Kane

Amir Nayyarhabibi

Kevin C Kahn

Farhad Mighani

Mark Snesrud

Rob Maffit

Haim Sadger

Joshi S Chandra

A method and apparatus for transceiving multiple service data from multiple communication services to a SONET/SDH communication system or network is provided. A SONET/SDH universal framer (SURF) bidirectionally provides communication between a SONET/SDH communication port and multiple service communication ports using their native data format. A provisioning register stores provisioning information describing the communication system and the communication ports. A SONET/SDH byte engine processes complex hierarchical SONET/SDH frames storing intermediate states when it changes to process a byte of data of a different STS-equivalent frame in a SONET/SDH STS-N frame. A service byte engine processes the multitude of service data formats and generally its intermediate states are restored, processed, and saved when it changes to process a different data stream or a different frame of data of a given service. An elastic storage means allows the SONET/SDH byte engine and the service byte engine to operate independent of one another in an asynchronous mode.

Method and apparatus for transceiving multiple services data simultaneously over SONET/SDH

A method and apparatus for transceiving multiple service data from multiple communication services to a SONET/SDH communication system or network is provided. A SONET/SDH universal framer (SURF) bidirectionally provides communication between a SONET/SDH communication port and multiple service communication ports using their native data format. A provisioning register stores provisioning information describing the communication system and the communication ports. A SONET/SDH byte engine processes complex hierarchical SONET/SDH frames storing intermediate states when it changes to process a byte of data of a different STS-1 equivalent frame in a SONET/SDH STS-N frame. A service byte engine processes the multitude of service data formats and generally its intermediate states are restored, processed, and saved when it changes to process a different data stream or a different frame of data of a given service. An elastic storage means allows the SONET/SDH byte engine and the service byte engine to operate independent of one another in an asynchronous mode.

A method and apparatus for transceiving multiple service data from multiple communication services to a SONET/SDH communication system or network are provided. A SONET/SDH universal framer (SURF) bidirectionally provides communication between a SONET/SDH communication port and multiple service communication ports using their native data format. A SONET/SDH byte engine processes complex hierarchical SONET/SDH frames storing intermediate states when it changes to process a byte of data of a different STS-1 equivalent frame in a SONET/SDH STS-N frame. A service byte engine processes the multitude of service data formats and generally intermediate states are restored, processed, and saved when the service byte engine changes to process a different data stream or a different frame of data of a given service.

Multi-PHY addressing from source to destination in which n-number of channels or ports are used in a PHY layer device for communication with a link layer device. A single link layer to a single-PHY layer topology and a single link layer to a multi-PHY layer topology comprising multiple ports or channels receives a plurality of channels groups. Status indication signal is provided on continuous basis for the direct status for up to a predetermined number of channels.

Method and system for multi-PHY addressing

A source synchronous clocking synchronizes data and clock signals transmitted between an ATM layer and a link layer. The source synchronous clocking includes a source clock domain in a first layer which includes a register having a first input for receiving a data signal, a second input for receiving a clock signal, and an output; and a buffer having an input for receiving the clock signal and an output, the buffer generating a delay that is substantially equivalent to a delay through the register. The source synchronous clocking further includes a destination clock domain in a second layer which includes a register having a first input and a second input, the first input of the register of the destination clock domain being coupled to the output of the register in the source clock domain.

Method and system for source synchronous clocking

The present invention includes a method and apparatus for prioritizing and scheduling ATM cells that are competing for a given time slot for transmission onto a network. A segmentation and reassembly controller establishes a data structure within a memory. The preferable data structure includes a virtual connection time table and a virtual connection parameter table that use linked lists to index to one another. The segmentation and reassembly (SAR) controller includes a sorter for determining the priority of the ATM cells and selecting one for a given time slot and a microcode engine to compute next scheduled time slot and adjust the virtual connection parameter table for a given virtual connection. Coupled to the microcode engine is a random access memory for storing microcode programs so that the SAR may be programmed to prioritize and schedule in a different manner.

Unified network cell scheduler and flow controller

The present invention teaches a new system for transferring data between a network and hosts coupled to the network. The system uses an adapter, that is coupled between the host and the network, to allow segmenting and reassembling cells directly in the host memory. The present invention also teaches a pipelined DMA architecture to overcome the problem of the interruption of the DMA operation when switching from one virtual circuit to the next. This architecture depends on fast access to a local memory used for storing buffer descriptors for each virtual circuit. In this architecture, a two stage pipeline is used with the first stage performing the local memory access while the second stage performs the DMA transfers. When the pipeline is filled, both stages will operate in parallel yielding significant gain in performance due to continuous operation of the DMA.

Growing community of inventors

Saratoga, CA, United States of America

Jay Sethuram