Sonics, Incorporated

Intel Corporation

Jay S Tomlinson

Drew Eric Wingard

Wolf-Dietrich Weber

Chien-Chun Chou

Lisa A Robinson

Geert Paul Rosseel

Ian A Swarbrick

Michael Jude Meyer

Nabil Masri

Thomas Wayne O'Connell

Robert P Adler

Krishnan Srinivasan

Stephen W Hamilton

Robert De Gruijl

Scott Carlton Evans

Kamil Synek

Doddaballapur N Jayasimha

Jeremy Chan

Chien Chun Chou

Eric A Geisler

Richard Aras

Geert-Paul Rosseel

Sricharan Kasetti

Chien Chum Chou

In one embodiment, a design tool for designing a system on chip (SoC) includes hardware mapping logic to automatically generate a channel mapping for a path between a first intellectual property (IP) logic of the SoC and a second IP logic of the SoC. The hardware mapping logic, based at least in part on user input of a source channel associated with the first IP logic, a sink channel associated with the second IP logic and at least one derivation parameter, is to generate the channel mapping according to one of a plurality of derivation algorithms. Other embodiments are described and claimed.

Method, apparatus and system for automatically performing end-to-end channel mapping for an interconnect

In one embodiment, a design tool for designing a system on chip (SoC) includes hardware logic to generate one or more configuration files for a fabric of a SoC to be designed by the design tool. This logic is configured, based at least in part on user input, to generate the one or more configuration files, according to at least one of: automatic derivation of all parameters of the fabric, according to a first user selection; manual input by a user of at least some parameters of the fabric and automatic derivation of at least other parameters of the fabric, according to a second user selection; and manual input by the user of the all parameters of the fabric, according to a third user selection. Other embodiments are described and claimed.

Method, apparatus and system for automatically deriving parameters for an interconnect

A method for routing information in a flexible routing network which connects disparate initiators and targets includes implementing a packetization logic at an interface between an initiator or a target and a routing network to receive transmission traffic from the initiator or the target and to packetize the transmission traffic into packets. Each packet includes header and body portions. Each of the header and body portions includes one or more standard sized transmission units. Each standard sized transmission unit includes control and payload sections. A payload section associated with the body portion includes one or more chunks. The method includes encoding the one or more chunks using a Common Data Format (CDF). All transmissions within the routing network are based on the CDF. The CDF facilitates narrow-to-wide and wide-to-narrow link width conversion without having to manipulate subparts of data fields in the transmission traffic.

Use of common data format to facilitate link width conversion in a router with flexible link widths

Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.

Various methods and apparatuses for estimating characteristics of an electronic systems design

Various methods and apparatuses for estimating characteristics of an electronic system's design

An embodiment includes a communication medium coupled to a plurality of the functional blocks in an integrated circuit. Three or more of the initiator functional blocks communicate with a target functional block by sending requests having an associated identifier to indicate a transaction stream that the request is part of. At least a first and a second of buffer are associated with the target functional block at an interface of the target functional block to the communication medium and receive requests having the associated identifiers from the three or more initiator functional blocks through a shared common connection point for the interface. The communication medium implements a mapping algorithm to map requests from a first initiator functional block as well as requests from a third initiator functional block to a first dedicated buffer based on the associated identifiers. The mapping algorithm also maps requests from a second initiator functional block to a second buffer based on the associated identifier.

Communications system and method with multilevel connection identification

Embodiments of apparatuses, systems, and methods are described for composing on-chip interconnects with configurable interfaces. A configurable interface includes a configurable agent and interface port. The configurable agent has a first input and a first output with the first input receiving a first communication. An input of a core receives the configurable agent's first output. The agent is configured for important inter-network characteristics such as topology, flooding control, clocking/reset, and performance enhancement.

Composing on-chip interconnects with configurable interfaces

A core block with a highly configurable interface such that the interface of the core can be optimally configured for the system the core is integrated into. In one embodiment the method consists of defining a configurable interface with different configuration options, capturing the specific core configuration through manual entry or through the use of a Graphical User Interface, and providing for software that combines the source description of the core with the configuration data to generate the core with an optimally configured logic and circuit interface.

Logic system with configurable interface

A method and apparatus of a configurable address mapping and protection architecture and hardware for on-chip systems have been described.

Method and apparatus for configurable address mapping and protection architecture and hardware for on-chip systems

A method and apparatus for on-chip inter-network performance optimization using configurable performance parameters have been described.

On-chip inter-network performance optimization using configurable performance parameters

A communication system and method with configurable posting points have been described.

Communication system and method with configurable posting points

A communication system. One embodiment includes at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection. A connection is a logical state in which data may pass between the first functional block and the second functional block. One embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a thread identifier that indicates a transaction stream that the data transfer is part of and a busy signal identified by the thread identifier. The busy signal is issued by the target functional block when resources will be unavailable to perform a transfer.

Communications system and method with non-blocking shared interface

Various methods and apparatuses are described in which an arbitration controller cooperates with arbitration logic. The arbitration controller has a plurality of inputs that receive one or more transactions from a plurality of blocks of functionality. The arbitration controller arbitrates requests for access to a shared resource amongst the plurality of blocks of functionality by implementing an arbitration policy. The arbitration policy groups the transactions from the plurality of blocks of functionality into global groups of transactions for servicing by that shared resource. All of the transactions in a first global group are serviced by that shared resource prior to servicing transactions in a next global group of transactions. The arbitration logic facilitates the arbitration policy. The arbitration logic includes cascaded arbitration units that hierarchically arbitrate for the shared resource. The topology of the functional blocks supplying the transactions to the inputs into the arbitration controller is capable of varying independently of the arbitration policy achieved by the collection of arbitration units.

Various methods and apparatuses for arbitration among blocks of functionality

A communication system. One embodiment includes at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection, wherein a connection is a logical state in which data may pass between the first functional block and the second functional block. One embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a connection identifier that indicates a particular connection that a data transfer is part of, and a thread identifier that indicates a transaction stream that the data transfer is part of.

A method and apparatus for speculative response arbitration to improve system latency have been described.

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San Jose, CA, United States of America

Jay S Tomlinson