International Business Machines Corporation

Lnternational Business Machines Corporation

Jay Robert Herring

Marvin J Rich

Scot H Rider

Derrick LeRoy Garmire

Gregory Michael Nordstrom

Patrick Allen Buckland

Craig Brian Stunkel

William Alan Thompson

Nicholas P Rash

Peter H Hochschild

Robert Francis Bartfai

Carl Alfred Bender

Tin-Chee Lo

Kevin J Reilly

John D Flanagan

Ronald A Linton

Rama Krishna Govindaraju

Mark G Atkins

Kevin J Gildea

Rajeev Sivaram

Richard A Swetz

Francis Alfred Kampf

Fu Chung Chang

Karen F Rash, Legal Representative

Tracy C Phillips

Hanhong Xue

Chulho Kim

Piyush Chaudhary

Aruna V Ramanan

Robert R Livolsi

Joseph M Hoke

Robert James Lynch

LeRoy R Lundin

John Divirgilio

Steven Louis Makow

Andrew Z Muszynski

Rama J Govindaraju

Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device. In response to detecting the failure in the first link, at an IO device end, the first set of lanes is switched with the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes.

Cable redundancy and failover for multi-lane PCI express IO interconnections

Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.

In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.

Efficient probabilistic duplicate packet detector in computer networks

A series of state transitions is indicative of performance of hardware service actions. A transition from, for instance, a disconnected state to a connected state for a hardware component is indicative of performance of a service action for the hardware component. Detection of this transition is automatic.

Facilitating detection of hardware service actions

A method is provided for packet flow control for a switching node of a data transfer network. The method includes actively managing space allocations in a central queue of a switching node allotted to the ports of the switching node based on the amount of unused space currently available in the central queue. In a further aspect, the method includes separately tracking unallocated space and vacated allocated space, which had been used to buffer packets received by the ports but were vacated since a previous management update due to a packet being removed from the central queue. Each port is offered vacated space that is currently allocated to that port and a quantity of the currently unallocated space in the central queue to distribute to one or more virtual lanes of the port.

Method for actively managing central queue buffer allocation

A system and method to provide injection of important data directly into a processor's cache location when that processor has previously indicated interest in the data. The memory subsystem at a target processor will determine if the memory address of data to be written to a memory location associated with the target processor is found in a processor cache of the target processor. If it is determined that the memory address is found in a target processor's cache, the data will be directly written to that cache at the same time that the data is being provided to a location in main memory.

System and method for intelligent software-controlled cache injection

Method, system and program product are provided for reducing size of memory required for a switching node's forwarding table by employing forwarding tables of different types to map received data packets addressed to downstream nodes and upstream nodes to appropriate output ports of the switching node. The method includes receiving a data packet at a data transfer node of a network and selecting a forwarding table from multiple types of forwarding tables accessible by the node based on an attribute associated with the received data packet, and mapping the data packet to an output port of the node utilizing the forwarding table selected from the multiple types of forwarding tables based on the attribute associated with the packet.

System and program product for facilitating forwarding of data packets through a node of a data transfer network using multiple types of forwarding tables

A system and method are provided in which communication adapters, which are used for the transfer of message packets from and amongst a plurality of data processing nodes, are provided with internal storage which is used to indicate the status of a particular adapter as a master, as a slave or as a backup up adapter. This information provides the adapters with the ability to be called into service to take over the operations of another adapter in the event of node or adapter failure.

Master-slave adapter

A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.

On-Chip AC self-test controller

Deadlocks are avoided in performing failovers in communications environments that include partnered interfaces. An ordered set of steps are performed to failover from one interface of a partnered interface to another interface of the partnered interface such that deadlocks are avoided.

Avoiding deadlocks in performing failovers in communications environments

A method is provided for reducing size of memory required for a switching node's forwarding table by employing forwarding tables of different types to map received data packets addressed to downstream nodes and upstream nodes to appropriate output ports of the switching node. The method includes receiving a data packet at a data transfer node of a network and selecting a forwarding table from multiple types of forwarding tables accessible by the node based on an attribute associated with the received data packet, and mapping the data packet to an output port of the node utilizing the forwarding table selected from the multiple types of forwarding tables based on the attribute associated with the packet.

Method for facilitating forwarding of data packets through a node of a data transfer network using multiple types of forwarding tables

A method and system for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation are provided. The method includes applying a long data capture pulse to a first test register in response to the system clock, applying an at speed data launch pulse to the first test register in response to the system clock, inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register, applying an at speed data capture pulse to a second test register in response to the system clock, inputting the logic path output to the second test register in response to applying the at speed data capture pulse to the second test register, and applying a long data launch pulse to the second test register in response to the system clock.

Method and system for an on-chip AC self-test controller

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Poughkeepsie, NY, United States of America

Jay Robert Herring