National Semiconductor Corporation

Fairchild Semiconductor Corporation

Jay R Chapin

Roy L Yarbrough

Thomas M Luich

Ronald B Hulfachor

Jeffrey B Davis

Michael G Ward

Donna Robinson-Hahn

Lifang Lou

A protective SCR integrated circuit device is disclosed built on adjacent N and P wells and defining an anode and a cathode. In addition to the anode and cathode contact structures, the device has an n-type stack (N+/ESD) structure bridging the N-Well and the P-Well, and a p-type stack (P+/PLDD) structure in the P-Well. The separation of the n-type stack structure and the p-type stack structure provides a low triggering voltage without involving any external circuitry or terminal, that together with other physical dimensions and processing parameters also provide a relatively high holding voltage without sacrificing the ESD protection robustness. In an embodiment, the triggering voltage may be about 8V while exhibiting a holding voltage, that may be controlled by the lateral dimension of the n-type stack of about 5-7 V.

Un-assisted, low-trigger and high-holding voltage SCR

An ESD protective triggering circuit for a triggering circuit for a solid state ESD protective device. The arrangement is to provide a controlled current to the protective device that triggers the device so that the device snaps-back and additionally the triggering device enables the parasitic transistor to participate in the draining of the ESD current. The triggering circuit also terminates the current to the protective device when the ESD voltage starts to fall. The triggering circuit can be used in any computer controlled electronics system.

Active power/ground ESD trigger

A power-up circuit with hysteretic characteristics for regulating the activation of one or more output buffers of an extended logic circuit. The hysteresis of the power-up circuit of the invention permits turn on of a switching transistor of the circuit at one threshold voltage level and maintains the active state of that switching transistor until a second lower threshold voltage level. The hysteresis is achieved by providing two separate and electrically isolated control paths that are connected to the control node of the switching transistor. The first control path includes a plurality of diode devices designed to regulate the power supply level required to turn on the switching transistor. The second control path also includes diode devices but in lesser numbers so that, once the switching transistor is turned on by the first control path, it remains on in spite of fluctuations at the power supply rail.

Hysteretic power-up circuit

A transient-eliminating circuit for minimizing simultaneous conduction through the pullup and pulldown transistors of a buffer circuit. In a buffer circuit used to translate logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail, in which the potentials of the two high-potential rails are not equal, the transient-eliminating circuit is coupled between the output stage and the input stage in such a way that the translator can be utilized independent of power-up sequencing and without any static current I.sub.CCt. The transient-eliminating circuit minimizes simultaneous conduction through the pullup and pulldown transistors of the translator by delaying the turn-on of the pulldown transistor until the pullup transistor is completely off. This is achieved in the preferred embodiment of the invention by coupling an NMOS transistor to the output of the translator circuit to act as an early pulldown on the output by using that NMOS transistor to control a PMOS transistor which is in turn used to control the pulldown transistor. A second NMOS transistor of the transient-eliminating circuit also acts to control the pulldown transistor by operating in the reverse mode of the first NMOS transistor so as to ensure that the NMOS transistor is completely off when required.

Circuit for reducing transient simultaneous conduction

A circuit for translating logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail in which the potentials of the two high-potential rails are not equal. The translator of the present invention is utilized in the transition from a 3V-supplied circuit to a 5V-supplied circuit, or vice versa, without any static current I.sub.CCt and regardless of the power-up sequencing. The static current is eliminated by isolating the output of the first stage of the translator, which is at the first high-potential power rail level, from all transistors of the second stage that are tied directly to the second high-potential power rail. In the preferred embodiment of the invention the transistors of the second stage that are powered by the second high-potential power rail are PMOS transistors and the isolation is achieved by linking those PMOS transistors to the first stage through a series of controlling NMOS transistors. In that way, the PMOS transistors will be completely turned off when necessary so as to avoid any undesirable conduction paths occurring due to differences in the potentials of the two high-potential power rails.

VCC translator circuit

According to the teachings of this invention, a novel sense amplifier is provided which includes a current steering transistor having its emitter connected to the collector of a current mirror transistor, its collector connected to the base of an output transistor, and its base driven by the input signal. With a low input signal, the emitter of the current steering transistor is pulled low, thereby pulling the base of the output transistor low. Conversely, when the input signal is high, and the current steering transistor ceases to operate in the active saturation mode and begins to operate in the inverse active saturation mode, thereby providing current from its base to its collector in order to turn on the output transistor.

Growing community of inventors

South Portland, ME, United States of America

Jay R Chapin