Agere Systems Inc.

Lucent Technologies Inc.

Lsi Corporation

Jay Patrick Wilshire

Bryan Schlieder

Shaun Patrick Whalen

Michael Richard Betker

Michael Samuel Shaffer

Sanjay Jinturkar

Alan Joel Greenberger

Ramesh V Peri

Han Nguyen

Lincoln A Fajardo

Aaron Louis Fisher

Harold J Wilson

Dale E Parson

Robert L Smigielski

James C Vollmer

Ning Li

Martin Trew

Swaminathan Venkatakrishnaprasad

Vijayalakshmi Kanthamneni

Donna M Nemshick

Wen N Wang

Tim Reinhard

Ravi Krishnaswamy

Steven Rothweiler

In an N+1 protection scheme for a router in a data or telecommunications network, a processor-based protection unit has a replica device handle, corresponding to each of the N working units, stored in the protection unit's local memory. Each replica device handle is an image of the connections provided by the corresponding working unit. In one implementation, upon detection of a failure of one of the working units, the router's controller unit sends a single command to instruct the protection unit to reconfigure itself using the corresponding locally stored replica device handle to assume the routing functions of the failed working unit.

N+1 protection using a processor-based protection device

Methods and apparatus are provided for evaluating the throughput limit of a communication system, such as a network node or system. A throughput limit of a communication system is evaluated by receiving a request to allocate at least one connection of a given data type; obtaining an assigned weight for the at least one connection, wherein the assigned weight is based on the throughput limit and a processing limit indicating a throughput of the communication system for the given data type within a given time window; and determining whether to allocate the at least one connection of a given data type based on whether a sum of the assigned weights for each existing allocated connection for each data type exceeds the throughput limit. The assigned weight for a given data type can be subtracted from the sum upon receiving a request to de-allocate a connection.

Methods and appratus for evaluating a utilization of a system that provides connections using a normalized bandwidth scheme

Techniques are disclosed for implementing software breakpoints in a processor system having at least one processor coupled to a main memory and associated with an instruction cache. A breakpoint code is inserted at a particular location in the instruction cache of at least a given one of the processors, and a control indicator associated with the particular location is set to a first state which allows the breakpoint code to be returned to the given processor from the instruction cache in response to a first fetch request directed to a corresponding address. Subsequently, the control indicator associated with the particular location is set to a second state which directs that a second fetch request to the corresponding address be serviced from the main memory. The control indicator state is then changed again after a determination has been made, from the control indicator having been set to the second state, that the second fetch request to the corresponding address will be serviced from the main memory.

Processor system with cache-based software breakpoints

Techniques are disclosed for implementing software breakpoints in a multiprocessor system having a number of processors each coupled to a main memory. In an illustrative embodiment, each of the processors has an instruction cache associated therewith. An instruction for which a breakpoint is to be inserted is retrieved from a corresponding instruction address in the main memory, and a breakpoint code is inserted at the instruction address in main memory. After the breakpoint code is executed by a given one of the processors, the retrieved instruction is stored in the corresponding instruction cache for that processor, and a use-once indicator is set. The use-once indicator is operative via cache control logic to clear a validity indicator associated with the instruction after a single fetch of the instruction from the instruction cache, such that subsequent attempts by the given processor to access the instruction as stored in the instruction cache will cause the processor to retrieve the breakpoint code at the instruction address in main memory.

Multiprocessor system with cache-based software breakpoints

An integrated circuit or other type of digital system including multiple processors is tested using a control mechanism which dynamically defines a group of processors subject to common control. The control mechanism receives one or more commands for each of the processors in the group, and delays issuance of one or more of the commands for the group until a designated group scan command is received for each of the processors in the group. The control mechanism may be in the form of a software-implemented chain manager which provides the above-noted group definition, command receipt and issuance delay operations, and subsequently delivers one or more of the test commands as a single serial bit stream to an IEEE 1149.1 hardware scan chain associated with the processors. The control mechanism can provide synchronous control for a group of homogeneous processors of the digital system, or pseudo-synchronous control for a group of heterogeneous processors of the digital system.

Control method and apparatus for testing of multiple processor integrated circuits and other digital systems

A system for debugging the computer program present in read-only memory (ROM) contains a debugger, a processor, read-only memory, a bus and a hardware debugging support module. The hardware debugging support module contains a first register called the range start register, a second register called the range end register and a comparator. The debugger uses a list of &ldquo;n&rdquo; user specified break points to divide a computer program into &ldquo;n&plus;1&rdquo; regions, each of which has a start address and an end address. The first register and the second register of the hardware debugging support module are programmed with the start address and end address of a region which contains a specific address. The comparator is connected to the first register and second register of the hardware debugging support module and is also connected to the bus which connects the read-only memory to the processor. The comparator monitors addresses traveling on the bus and causes the hardware debugging support module to interrupt the processor and transfer control of the computer program to the debugger if a specific address traveling on the bus does not fall within the range defined by the first register and the second register. The debugger then searches the remaining &ldquo;n&plus;1&rdquo; regions to see if the specific address lies within a second region. If such a region is found, then the start address and end address of that second region are entered into the first register and the second register and the computer program is run. However, if such a region is not found, then the computer program has reached a break point and the debugger transfers control of the program to the user. The computer program can then be single stepped to execute the instruction at which the break point was placed to obtain an output address. The start address and end address of the region that contain this output address are programmed into the first register and the second register and the computer program is run. This process is repeated until the entire computer program has been executed.

System for debugging (N) break points by dividing a computer program to (n&plus;1) regions each contains no break point and using two registers to define the start and end addresses of each region

There is disclosed an integrated circuit including a digital processor having EEPROM and a control register. The digital processor is capable of receiving data to be programmed into the EEPROM and is capable of programming the data into the EEPROM. The digital processor includes a control register for receiving bits to control a write line and an erase line. The digital processor also includes a processor core coupled to the control register by a data bus, the digital processor is coupled to the EEPROM by a ROM address bus and a RAM data bus. The EEPROM memory location identified by the ROM address bus is programmed to retain data latched onto the RAM data bus. This is achieved by the digital processor writing control bits to the control register to enable the write line for a write operation of sufficient duration to assure that the data on the RAM data bus is retained in the EEPROM memory address that is enabled.

Digital processor with embedded eeprom memory

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Pennsburg, PA, United States of America

Jay Patrick Wilshire