Raytheon Company

Massachusetts Institute of Technology

Jay P Sage

Arthur M Cappon

John D Collins

A shift register having a first bistable latching circuit operable for switching between a low voltage state and a high voltage state in response to receiving an input current and a first clock voltage pulse. A second bistable latching circuit operable for switching from said low voltage state to the high voltage state in response to receiving a switching current induced from the first bistable latching circuit and a second clock voltage pulse. A clock voltage pulse source operable for successively providing clock voltage pulses in phase sequence to the first and second bistable latching circuits. A coupling circuit coupled between the first and second bistable latching circuits and having electrical characteristics such that the coupling circuit generates the switching current for a predetermined voltage drop across the coupling circuit in response to the first bistable latching circuit being in the high voltage state, the coupling circuit generating currents of lesser value than the switching current for voltage drops which are lesser or greater than the predetermined voltage drop.

Tunnel diode shift register utilizing tunnel diode coupling

A signal processor having a plurality of charge transfer devices adapted for coupling to an input signal source. Each one of such devices produces a sample of the input signal in response to a sampling signal. An input shift register having a plurality of serially coupled stages is provided, each one of such stages being coupled to a corresponding one of the charge transfer devices. Circuitry is included for enabling the sampling signal to be sequentially produced at an output of each one of the serially coupled stages, enabling sequential samples of the input signal to be produced in corresponding ones of the charge transfer devices.

Signal processor

A charge transfer device having a source diffusion region, an isolation gate region, a reference voltage gate region and an input signal gate region disposed contiguously along such device, the isolation gate region being adapted for coupling to a pulse voltage source, the duration of such pulse being related to a predetermined sampling interval (and therefore related to the bandwidth of an input signal being sampled), the reference voltage gate region being adapted for coupling to a reference voltage source and the input signal gate region being adapted for coupling to the input signal. During each clock interval prior to the sampling interval the source diffusion region is pulsed, thereby enabling charge to pass from such region into the reference voltage gate region and the input gate region. During the sampling interval the potential energy level of the isolation gate region is lowered to enable equilibration of the potential of the charge in the input gate region with the potential in the reference voltage source region, the charge in such input gate region thereby being proportional to the input signal level during the sampling interval. At the end of the sampling interval the potential energy level of the isolation gate region is raised to isolate the source diffusion region from the input gate region and thereby inhibit charge flow from the input gate region to the source diffusion region if the input signal level varies prior to the time at which the charge in the input gate region is transferred to the first storage stage of the device.

Charge transfer device input circuitry

A method of storing electric charges in a metal-nitride-oxide-semiconductor memory element by setting the threshold voltage of the element at any of a substantial number of voltages by applying both a DC voltage corresponding to the analog voltage to be stored and an AC voltage which is gradually reduced.

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Newton, MA, United States of America

Jay P Sage