Qualcomm Incorporated

Jay Madhukar Shah

Animesh Datta

Mohamed Hassan Abu-Rahma

Martin Saint-Laurent

Ramaprasath Vilangudipitchai

Seid Hadi Rasouli

Prayag Bhanubhai Patel

Kamesh Medisetti

Chethan Swamynathan

Peeyush Kumar Parkar

Sachin Bapat

HariKrishna Chintarlapalli Reddy

Ananth Haliyur Gopalakrishna

Vijayalakshmi Ranganna

A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

Flip-flop with reduced retention voltage

A MOS device includes a first FinFET having a first transistor source, drain, gate, and set of fins, and includes a second FinFET having a second transistor source, drain, gate, and set of fins. The MOS device further includes a gate interconnect extending linearly to form and to connect together the first and second transistor gates. The MOS device further includes a first interconnect on a first side of the gate interconnect that connects together the set of first transistor fins at the first transistor drain and the set of second transistor fins at the second transistor source, a second interconnect on a second side of the gate interconnect that connects together the set of first transistor fins at the first transistor source, and a third interconnect on the second side of the gate interconnect that connects together the set of second transistor fins at the second transistor drain.

Stacked common gate finFET devices for area optimization

A standard cell CMOS device includes a first power rail extending across the standard cell. The first power rail is connected to one of a first voltage or a second voltage less than the first voltage. The device further includes a second power rail extending across the standard cell. The second power rail is connected to an other one of the first voltage or the second voltage. The second power rail includes a metal x layer interconnect and a set of metal x&#x2212;1 layer interconnects connected to the metal x layer interconnect. The device further includes a set of CMOS transistor devices between the first and second power rails and powered by the first and second power rails. The device further includes an x&#x2212;1 layer interconnect extending under and orthogonal to the second power rail. The x&#x2212;1 layer interconnect is coupled to the set of CMOS transistor devices.

Adaptive standard cell architecture and layout techniques for low area digital SoC

Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

Circuit and layout techniques for flop tray area and power otimization

Growing community of inventors

Bengaluru, India

Jay Madhukar Shah