International Business Machines Corporation

Globalfoundries Inc.

Jay M Shah

Michael Patrick Chudzik

Deleep R Nair

Vijay Narayanan

Carl John Radens

Christopher V Baiocco

Terence B Hook

Toshiaki Kirihata

Kenneth Jay Stein

Krishnan Santhana Rengarajan

Ramesh Raghavan

Balaji Jayaraman

Melanie J Sherony

Helen Wang

Janakiraman Viraraghavan

Rajesh Reddy Tummuru

Thejas Kempanna

Navin Agarwal

Chendong Zhu

Aditya S Auyisetty

Approaches for a memory including a cell array are provided. The memory includes a first device of the cell array which is connected to a bitline and a node and controlled by a word line, and a second device of the cell array which comprises a third device which is connected to a source line and the node and controlled by the word line and a fourth device which is connected between the word line and the node. In the memory, in response to another word line in the cell array being activated and the word line not being activated to keep the first device in an unprogrammed state, the third device isolates and floats the node such that a voltage level of a gate to source of the first device is clamped down by the fourth device to a voltage level around zero volts.

Disturb free bitcell and array

Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.

Method and structure to reduce FET threshold voltage shift due to oxygen diffusion

At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.

Oxygen scavenging spacer for a gate electrode

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.

Self-limiting oxygen seal for high-K dielectric and design structure

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Poughkeepsie, NY, United States of America

Jay M Shah