Unisys Corporation

Dialogic Corporation

Intel Corporation

Diaogic Corporation

Jay L Gerbehy

Richard P Graber

Kenneth J Burkhardt, Jr

Theodore J Skapinetz

David Gish

Brian Peebles

Gerald Lebizay

Nicholas Zwick

Don V Massa

Chester Juall

Patrice M Bermond-Gregoire

Patrice M Bremond-Gregoire

Louis J Francz

Charles R Walden Jr

Multiple boards are connected within a chassis, using a multi-port Target Channel Adapter (TCA). Data is transported from a TCA on a board directly to a TCA on another board through a meshed backplane. The meshed backplane is equipped to mount boards via connectors and may consist of a fabric of copper conductors or optical fibers. Communication from TCA to TCA requires placing ports on each individual TCA along with the appropriate input and output buffering. A multi-port TCA capable of performing multiple bridging functions simultaneously i.e., bridging from a high speed serial meshed backplane to multiple local busses, i.e., Gigabit Ethernet, Fibre Channel, and TCP/IP devices, is referred to as a Fabric Interconnect Chip (FIC).

Multi-port high-speed serial fabric interconnect chip in a meshed configuration

A signal computing bus (SCbus) includes two bus structures: (a) a synchronous TDM data transport referred to as a data bus and (b) a serial message passing bus referred to as a message bus. The following three groups of functions are performed using the SCbus: (a) data transport over the data bus, (b) message passing over the message bus, and (c) data and message bus control. In a preferred embodiment, the data bus utilizes: 2 clocks, 1 frame pulse, 16 data busses, and 1 clock control (the clock control signal enables access to the bus and automatic switching from one clock master to another when an error is detected) and the message bus is fabricated using a master HDLC protocol with contention resolution.

Signal computing bus

TDM bus and, in particular, a PCM Expansion Bus (PEB): (a) which permits a multiplicity of apparatus to monitor a TDM signal simultaneously and (b) wherein various timing and control signals are provided in a manner that minimizes the hardware needed by the apparatus for identifying, i.e., decoding, various channels in the TDM signal for accessing and inserting information therein.

TDM expansion bus

Interprocessor message communication and synchronization apparatus and method for a plurality of processors connected to a system bus. The message communication photocol involves utilizing an array of mailbox locations associated with the processors, respectively, and located in common memory accessible to all of the processors. A processor desiring to send a message to another processor inserts the message into its mailbox along with the address of the other processor. The sending processor interrupts the receiving processor which, in response to the interrupt, scans the mailboxes to find the mailbox with its address therein thereby receiving the message. The interrupt is effected by the sending processor broadcasting an input/output write instruction on the system bus along with the address of the receiving processor and a data field representative of the interrupt to be transmitted. Apparatus associated with the receiving processor includes a decoder that responds to the input/output write instruction to enable a register when the address transmitted on the bus matches its address. The enabled register receives the data signals from the bus to set therein the appropriate interrupt signal represented by the data. The stages of the register are connected to the associated interrupt input of the other processor.

Intercomputer communication control apparatus and method

Interprocessor message communication synchronization apparatus and method for a plurality of processors connected to a system bus where one processor desiring to send a control signal to another processor, broadcasts an input/output write instruction on the system bus along with the address of the receiving processor and a data field representative of the control signal to be transmitted. Apparatus associated with the receiving processor includes a decoder that responds to the input/output write instruction to enable a register when the address transmitted on the bus matches its address. The enabled register receives the data signals from the bus to set therein the appropriate control signal represented by the data. The stages of the register are connected to the associated control signal inputs of the other processor. In this manner the one processor may transmit a message synchronizing interrupt to the other processor.

Intercomputer communication control apparatus & method

A Call Filter System (CFS): (1) logically interfaces between a public telephone network and business customer premises equipment; (2) automatically processes incoming and outgoing calls which are amenable to such intervention; and (3) enlists the aid of human intervention on calls requiring such intervention. The CFS includes a network line interface (NLI) for receiving calls from and placing calls to the public telephone network; a premises line interface (PLI) for receiving calls from and placing calls to the business customer premises equipment; a voice processing means (VPM) which is switchably interconnected to the NLI and/or the PLI for translating audio signals transmitted thereto from the NLI or PLI and for transmitting audio signals to the NLI or PLI; a connection and switching means (CSM) for connecting and switching the NLI to either the PLI or VPM and for connecting and switching the PLI to either the NLI or VPM; and a controller for directing the activities of the NLI, PLI, VPM and CSM to automatically process incoming calls to and outgoing calls from the CFS.

Automated call filter

Growing community of inventors

Califon, NJ, United States of America

Jay L Gerbehy