Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Jay Kumar

Zvonimir Z Bandic

Won Ho Choi

A first write operation is received. The first write operation includes a SET operation. The SET operation is configured to place a cell of the non-volatile memory (NVM) device in a relatively low-resistance state. A second write operation is received. A first electrical pulse is applied to a first cell of the NVM device. The first electrical pulse is applied to place the first cell in the relatively low-resistance state. A second electrical pulse is applied to a second cell of the NVM device. The second electrical pulse is applied before the first electrical pulse has concluded. The second cell and the first cell are both within a single tile of the NVM device.

Overlapping write schemes for cross-point non-volatile memory devices

A storage device includes a cross-point non-volatile memory (NVM) device that includes a first subset of cells. Cells of the first subset of cells may share either a bitline or a wordline. There may be at least one buffer cell on a respective bitline or wordline between each adjacent pair of cells from the first subset of cells. The storage device includes a control module. The control module is configured to receive a set of I/O operations. The control module is configured to execute a first subset of the set of I/O operations in parallel across the first subset of cells of the cross-point memory component. The control module may execute the first subset of the set of I/O operations such that I/O operations are not executed at the respective buffer cells.

Block erase schemes for cross-point non-volatile memory devices

Systems and methods for improving the performance of a non-volatile memory array during a memory operation by concurrently applying two different selected word line voltages to two different word lines within the non-volatile memory array are described. The memory operation may comprise a write operation or a combination of SET and RESET operations. The memory array may include a first word line connected to a first set of memory cells, a second word line connected to a second set of memory cells, and a third word line connected to a third set of memory cells. During the memory operation, the first word line may be set to a first selected word line voltage (e.g., 3V), the second word line may be set to a second selected word line voltage (e.g., 0V), and the third word line may be set to an unselected word line voltage (e.g., 1.5V).

Biasing scheme for multi-layer cross-point ReRAM

A storage device includes an interface, NVM device, and control module. The control module may be configured to receive a first write operation and a second write operation. The first write operation comprises a SET operation configured to place a cell of the NVM device in a relatively low-resistance state. The control module may be further configured to execute the first write operation by causing an electrical pulse to be applied to a first cell of the NVM device to place the first cell in the relatively low-resistance state. The control module may be further configured to execute the second write operation by causing an electrical pulse to be applied to a second cell of the NVM device before the first electrical pulse has concluded. A single tile of the NVM device includes the first cell and the second cell.

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Saratoga, CA, United States of America

Jay Kumar