Intel Corporation

Altera Corporation

Jay J Sturges

Richard P Vireday

David I Poisner

Randy C Steele

Gregory B Hibdon

Greg Hibdon

A method involves operations for executing source code instructions expressed in a programming language. The operations comprise receiving a series of source code instructions expressed in a programming language, wherein at least one of the source code instructions includes a command and one or more arguments. In response to receiving the source code instruction, at least part of a stack-based execution stream is built. The stack-based execution stream is also executed. The operation of building at least part of a stack-based execution stream involves storing the instruction's argument on a stack, determining an address for an object code routine corresponding to the instruction's command, and storing the address for said object code routine on the stack. Other embodiments are described and claimed.

Programmable interpretive virtual machine

The shared computer system memory is partitioned between system memory and frame buffer memory. The frame buffer is configured as the top-most portion of the shared memory. A virtual memory manager controls access to the system portion of the shared memory. A virtual frame buffer device controls access to the frame buffer portion of the shared memory. While a frame buffer is defined, graphics operations, such as commands data, generated by a host CPU are routed to the memory manager by the virtual frame buffer device driver. Other graphics operations, such as those provided by peripheral devices interconnected via a PCI bus, are executed by the graphics controller. If an input buffer of the memory controller is full, graphics operations issued by the host CPU are rerouted onto the PCI bus for execution by the graphics controller. If no frame buffer is defined, then all graphics operations generated by the host CPU as well as all other PCI bus masters are transmitted over the PCI bus and are executed by the graphics controller. While a frame buffer is defined, memory access protocols and cache coherency protocols, described herein, are employed to prevent corruption of the data within the frame buffer portion of the shared memory. In one embodiment, the memory controller and the graphics controller both access the shared memory through a single interface bus. In an alternative embodiment also described herein, the shared memory is physically divided into two portions. The memory controller is interconnected by a first interface bus to both portions of the shared memory. The graphics controller is connected to only the second portion of the memory which is configured to include a frame buffer. As such, the memory controller may access system memory contained within the first portion of the shared memory while the graphics controller is accessing the frame buffer. In another alternative embodiment described herein, no graphics controller is provided. Rather, all graphics operations are performed directly by the host CPU. A frame buffer refresh unit takes the place of the graphics controller.

Method and apparatus for managing access to a computer system memory shared by a graphics controller and a memory controller

A programmable interpreter for creating, interpreting, and executing a programming language. The present invention is a virtual processor that eliminates interpretation of pseudo code typical of common interpretive engines. The preferred embodiment of the present invention includes a computer system comprising a bus communicating information, a processor, and a random access memory for storing information and instructions for the processor. The processing logic of the preferred embodiment is operably disposed within the random access memory and executed by the processor of the computer system. A command stream, comprising a command identifier or function name in combination with a string of arguments, is a typical input for the processing logic of the present invention. Upon activation of the processing logic of the present invention, a parser is executed to manipulate the input command stream and produce an execution stream with a processing component identifier corresponding to the specified command. The command is then executed indirectly and a pointer is updated to point to the next command in the execution stream. Arguments for commands are pushed on to and popped from a stack. Results from the execution of commands are pushed onto a stack. For commands that define a new function or procedure, frame data is maintained to preserve the context in which the new function or procedure is executed. Each command in the stream is interpreted in this manner until the end of the execution stream is reached.

A method and apparatus for dynamically allocating system memory using a binary tree organized in an address and size dependent manner. Within the prior art, dynamic memory allocation methods were not portable to virtual memory addressing systems wherein local memory and system memory were joined in a continuous region of linear addresses. The allocation method of the present invention utilizes a binary tree of free memory block headers, corresponding to free memory blocks. Each free memory block header has an address field and a translation table field. The address field corresponds to a virtual address of the free memory block. The translation table field points to an entry within a translation table that is used to map the virtual address to a block in system memory.

Method and apparatus for dynamic memory management by association of

A computer system having a shared memory accessible by a memory controller and a graphics controller is described. A portion of the shared memory is selectively defined as a frame buffer. Graphics operations provided by a client device are routed through the memory controller if a frame buffer is created. If no frame buffer is created, the graphics commands are routed through the graphics controller.

Method and apparatus for managing access to a computer system memory

The computer system includes a stereo audio circuit a universal serial bus (USB) controller, or other isochronous device controller. Left front and right front stereo audio channels are routed through the audio circuit to a pair of stereo speakers. One or more surround sound channels, perhaps including left rear and right rear channels, are routed through the USB controller to one or more USB peripheral surround sound speakers. The audio circuit and the USB controller operate from separate asynchronous clocks. A variety of techniques are disclosed for maintaining synchronization of the audio signals routed through the audio circuit and through the USB controller despite possible clock skew between the asynchronous clocks. Method and apparatus embodiments of the invention are disclosed.

Method and apparatus for integrating three dimensional sound into a

In a computer system having a CPU coupled to a memory wherein the memory is logically divided into a number of logical units, each having a number of memory words, a free memory block header list having a number of free memory block headers, one for each free memory block of a memory pool having a number of the memory words, is provided for tracking free memory blocks in the memory pool. The free memory block headers are organized as a Cartesian binary tree. The free memory block header list is used and maintained to control dynamic allocation and deallocation of free and allocated memory blocks of the memory pool. The memory pool is designed to have a memory pool size in multiples of the memory's logical units. All memory requests are rounded to multiples of the memory's word size. As a result, free and allocated memory blocks of the memory pool may be dynamically allocated and deallocated independent of how the memory is addressed, in particular, whether the memory is virtually or statically addressed.

A field programmable gate array in which the pattern of a first smaller switch matrix is continued into a number of other smaller reduced switch matrices necessary to provide full coverage for all of the input conductor combinations at the output conductors.

Method and apparatus for routing in reduced switch matrices to provide

A deterministic method and apparatus for defining the size and switch assignments of a switch matrix. The method operates on a switch matrix having a number of inputs (N) and a number of outputs (M). When constructing the switch matrix, there will be M columns in the matrix. The method determines a minimum number of rows (R) for the switch matrix. The resultant general purpose R.times.M switch matrix allows any combination of a subset of the N inputs, with up to M members, to be assigned to the outputs. The resultant R.times.M switch matrix will be smaller than an N.times.M switch matrix.

Deterministic method and an apparatus for minimal switch circuits

An integrated circuit including a plurality of individual boundary scan circuits each associated with a separate portion of the circuitry of the integrated circuit. The registers of the individual boundary scan circuits are joined to provide a series boundary scan register chain in which individual portions of the circuitry included within the integrated circuit may be individually manipulated.

Apparatus for configuring a subset of an integrated circuit having

A logic simulator for optimal configurability of combinatorial and sequential logic circuits in a simulated behavioral form. The present invention contains process oriented functional blocks with event posting to eliminate unnecessary evaluations in logic simulation. Also, the present invention manages a process to logic signal(s) and logic signal to process(s) sensitivity relationship(s) which reduces the traditional overhead of event scheduling and stabilization. The processing logic of the preferred embodiment is operably disposed within the random access memory and executed by the processor of a computer system. Upon activation of the present invention and initialization of all signals, a test is performed to determine if the logic network being simulated is in a stable condition. If the logic network is not stable, a loop is initiated for propagating signals and updating signal states throughout the logic network. Once the logic is propagated, the new state for all signals for which a state transition has occurred is set. Once the new states of signals have been set, a test is performed to determine if a new state has been encountered. A loop continues as long as signals transition to a new state. When a new state is not encountered, but the logic network has still not stabilized, a new state is forced and a new loop iteration is initiated. These loop iterations continue until the logic network stabilizes and simulation processing terminates.

Process oriented logic simulation having stability checking

A deterministic routing method for switch matrices. The routed matrix receives N input signals and produces M output signals on M output columns. The method of the present invention has three steps. First, each of the M output columns in the switch matrix is searched for each of N separate input signals. Secondly, each of the N inputs is assigned to its located column. If all of the N inputs cannot be assigned to one of the M columns, the set of inputs is shifted and the steps are repeated until all of the N inputs are routed.

Deterministic routing method for minimal switch circuits

A method in which the boundary-scan circuitry of a boundary-scan chain is placed in a first condition in which each bit of a series of bits will traverse a path through an equipment identification register if one exists or will require one clock to traverse each device in the boundary-scan chain in which no complete identification register exists. A first recognizable series of bits is sent through the chain and the beginning of the series of bits is detected at the output of the chain while a count is kept at the output to determine the number of individual boundary-scan circuits in the chain. The count is incremented by one for each identification register traversed or for each circuit which has no such complete register. The boundary-scan chain is then placed in a second condition in which each bit of a series of bits will traverse the instruction registers of the individual boundary-scan circuits in the boundary-scan chain, and a second recognizable series of bits is sent through the chain and counted until the a detectable portion of the second series of bits appears at the output of the boundary-scan chain. This count indicates the total number of bits in the instruction registers in the chain.

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Orangevale, CA, United States of America

Jay J Sturges