Avago Technologies International Sales Pte. Limited

Broadcom Corporation

Lsi Logic Corporation

Jay Edward Ackerman

Mark David Rutherford

Ryan Michael Desrosiers

John Lynn McNitt

Russell Eliot Radke

Kevin Vannorsdel

Yongjie Jiang

John S Walley

Pieter Vorenkamp

Rishi Agarwal

Marc Keppler

Arun Palaniappan

Ryan Desrosiers

Michael Owen Baker

Xuezhen Wang

Michael Braiman

Prasanna Obala Bhuvanesh

A structure is described which includes two amplifiers in parallel. A first amplifier is considered an always-on amplifier. The always on amplifier provides continual measurements of a current (Isns) across an integrated polysilicon resistor for one or more analog control loops. A second amplifier is considered a switched amplifier. The switched amplifier provides measurements of the current (Isns) for one or more digital control loops. The switched amplifier is switched by one or more switches for performing offset measurements with high accuracy.

Current sensing circuit with integrated resistor and dual sense amplifiers

One or more layout techniques may be used to balance a current sense circuit. The current sense circuit may include upstairs resistors for an amplifier which are formed of polysilicon material. The upstairs resistors may be arranged symmetrically about one or more stress gradients for improving an accuracy of the current sense circuit. The stress gradients may include stress gradients about an axis and stress gradients from a die edge.

Layout for integrated resistor with current sense functionality

An integrated circuit for measuring current while receiving wireless power is described. The integrated circuit measures a current across a resistor by an amplifier. A gain of the amplifier is based on a pair of matched upstairs resistors and a pair of matched downstairs resistors. The pair of matched upstairs resistors may include an offset in resistance. The integrated circuit includes a switch matrix with switches coupled between the integrated resistor and the pair of matched upstairs resistors. The offset for the pair of matched upstairs resistors may be measured by selectively controlling the switches.

Current sensing circuit with integrated resistor and switch matrix

A system may include an adapter, a charger, and a connector. The adapter is configured to receive an alternating current (AC) signal and generate an adapter signal, the adapter signal being generated based on an up-conversion of the AC signal. The charger is configured to generate a direct current (DC) signal from the adapter signal using one or more energy storage elements and supply the DC signal to a load, in which the adapter signal has a voltage greater than that of the DC signal. The connector is configured to couple the adapter and the charger. In some aspects, the adapter signal is adjusted based on one or more measurements of the DC signal at an output of the charger to maintain a target power for charging the load.

Battery charging architectures

A converter includes a first circuit. The first circuit includes a first input that receives a power supply signal, a second input that receives a first signal, and a first output that outputs a second signal having an amplitude that is based on a frequency of the first signal. The first signal is based on an error value and a third signal, and the third signal is independent of feedback of the first circuit. The converter also includes a second circuit having a second output coupled to the second input and that outputs the third signal. The second circuit nonlinearly adapts the third signal based on the power supply signal and a reference signal.

Methods and devices for operating converters

A multi-loop voltage regulator with load tracking compensation includes a first closed-loop feedback network configured to receive a supply voltage from a power supply and drive an output voltage that is smaller than the supply voltage to a load. The multi-loop voltage regulator includes a second closed-loop feedback network connected to the first closed-loop feedback network and configured to regulate the output voltage between a first supply voltage rail and a second supply voltage rail for a given load current, in which the second closed-loop feedback network produces a gain that is greater than that of the first closed-loop feedback network. The multi-loop voltage regulator also includes a load tracking compensation circuit configured to detect a load current, and to increase the gain of the second closed-loop feedback network based on a dominant pole in the second closed-loop feedback network being a function of the detected load current.

Multi-loop voltage regulator with load tracking compensation

A circuit for a switching charger includes multiple input supply nodes, and a number of charging paths. Each input supply node is connectable to a power source. Each charging path may include a middle node connected to a coupling switch and a pass transistor. The coupling switch may be configured to activate a corresponding charging path of the charging paths. A pre-charging switch may be coupled to a corresponding middle node of each charging path. The pass transistor of an activated one of the charging paths may be configured to provide a switching voltage at an input of a charging sub-circuit. The pre-charging switch may be configurable to pre-charge a middle node of a non-activated path to a high voltage to prevent an unwanted high current passing through a body diode of a corresponding pass transistor of the non-activated path.

Pre-charging mechanism for multi-input switching charger

The present application discloses various implementations of a power management unit (PMU) suitable for use in a mobile device. In one exemplary implementation, such a PMU includes a gain control block configured to control an oscillator coupled to the PMU. The gain control block is further configured to control a clock output stage of the PMU. The PMU also includes a signal protection circuit coupled to an input of the gain control block. The signal protection circuit is configured to preserve clock signals produced by the clock output stage during a transition to a standby mode.

Power management unit including a signal protection circuit

A system and method are provided for safely recharging a battery. A current source is coupled to a node and configured to produce a current. The battery is coupled to the node, and is configured to recharge during a recharging cycle based on receiving the current through the node. An overvoltage protection system is coupled between the node and the current source, and configured to disable the current source when a voltage at the node exceeds a threshold value. For example, the current source may be substantially instantaneously disabled when this occurs.

Overvoltage protection utilized when a battery is removed from a system

A current-mode peak detector circuit is disclosed. The current-mode peak detector circuit includes an input transistor for receiving an input current that impresses a voltage on a control node, a pair of transistors for providing an output current in response to the voltage at the control node, and a decay control circuit for controlling the decay of the voltage at the control node such that the output current is representative of a peak value of the input current signal. A clamp circuit may be provided for clamping the input voltage to a predetermined level. All of the elements of the current-mode peak detector circuit may be realized using transistors for facilitating integration of the current-mode peak detector circuit on an integrated circuit. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other researcher to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Current-Mode Peak Detector

A circuit and method for generating a generally logarithmic transfer function based upon switching signals. The circuit includes a plurality of transistors and a switch operatively connected to each transistor in the programmable set. A line is in communication with each switch for carrying switching signals thereto thereby selecting which of the transistors will contribute to the generally logarithmic function. Preferably, the circuit is a portion of a programmable gain amplifier, and a digital code controls the gain. The gain can be generally logarithmic as a result of which transistors which are selected to contribute to the generally logarithmic transfer function. For example, there may be a plurality of sets of transistors where the values of the transistors in each set are such that when all the transistors of the set are selected to contribute to the generally logarithmic gain, the set of transistors provides a gain having a value approaching m. Each of the transistors in the set has a value which is generally a multiple of 1/2 m.

Growing community of inventors

Fort Collins, CO, United States of America

Jay Edward Ackerman