Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Jay D Reeves

Douglas Todd Hayden

Dale R Kopf

Todd Hayden

Lyle D Kraft

Systems and methods for backup of data in redundant data storage systems. In this regard, one embodiment can be broadly summarized by a representative system that copies a block of data from a primary storage unit to a primary backup storage unit using a primary addressing sequence that begins with a first start address; and substantially concurrently copies a second block of data from a secondary storage unit to a secondary backup storage unit using a secondary addressing sequence that begins with a second start address. Another embodiment can be described as a method wherein the first start address is the same as the second finish address; the primary addressing sequence uses an incrementing count, and the secondary addressing sequence uses a decrementing count. Other systems and methods are also provided.

Procedure to reduce copy time for data backup from short-term to long-term memory

A method for connecting an interface to a serial bus is provided comprising the steps of sensing at least one identification line for the interface, identifying an interface type from the at least one identification line, and switching the interface to or from a serial bus depending on the interface type identified. The at least one identification line specifies at least one serial type of interface and at least one non-serial type of interface. Preferably, the method further comprises the step of switching the interface off the serial bus based on a criteria.

Method for connecting gigabit interface converters with serial identification capability into an active two-wire serial bus

A method for securing port bypass circuit settings is presented comprising issuing one or more command(s) to one or more inputs of a general purpose input/output (GPIO) system, wherein the command(s) cause a first output of the GPIO system associated with a first input of the multiple inputs to issue a control signal to a latch associated with a port bypass circuit (PBC) addressed in the received command(s), and a second output of the GPIO system associated with a second of the multiple inputs of the GPIO system to issue a clock signal to a latch associated a PBC addressed in the received command(s). If command(s) received at the first and second inputs are consistent with changing the state of a common PBC, the control signal and the clock signal are sent to a single latching device, which latches the control signal to the addressed PBC changing the state of the PBC. If the command(s) are not consistent, the control and clock signal(s) are not received by a common latch, and the PBC states remain unchanged.

Architecture and related methods facilitating secure port bypass circuit settings

An EMI shield that utilzes perforated dimples or other features configured to reflect electromagnetic radiation while simultaneously permitting air flow through the shielding material.

Electromagnetic interference shield

A system includes multiple modules, each powered by a different power source, and a status indicator for a first of the modules. Any of the multiple modules can drive the status indicator. Each of the modules monitors the operation of the first module, driving the status indicator when the first module fails. Thus, even if a failure within the first module prevents the first module from driving the status indicator (e.g., a power failure), the status indicator is still driven by a second module.

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Meridian, ID, United States of America

Jay D Reeves