Qualcomm Incorporated

Jay Chunsup Yun

Andrew Evan Gruber

Rahul Gulati

Donghyun Kim

Brendon Lewis Johnson

Alex Kwang Ho Jong

Guofang Jiao

Chong U Lee

Vineet Goel

John Hyunchul Hong

Yun Du

Jian Jim Ma

Alexei Vladimirovich Bourd

Tallis Young Chang

Robert Sean Daley

Liang Li

Frederick Duke Kim

Anshuman Saxena

Javier Ignacio Girado

Chun Yu

Angus Dorbie

Elina Kamenetskaya

Bo Zhang

Vijay Ganugapati

Xujie Zhang

The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.

Self-test during idle cycles for shader core of GPU

A graphics processing unit (GPU) of a GPU subsystem of a computing device operates in a first rendering mode to process graphics data to produce a first image. The GPU operates in a second rendering mode to process the graphics data to produce a second image. The computing device detects whether a fault has occurred in the GPU subsystem based at least in part on comparing the first image with the second image.

Diverse redundancy approach for safety critical applications

Techniques of this disclosure may include processing data using one or more processors to produce a first image, including storing intermediate first results of processing the data in at least one internal memory of the one or more processors according to a first memory access pattern, processing the data using the one or more processors to produce a second image, including storing intermediate second results of processing the data in the at least one internal memory of the one or more processors according to a second memory access pattern, wherein the second memory access pattern is different than the first memory access pattern, comparing the first image to the second image, and generating an interrupt if the comparison indicates that the first image is different than the second image.

Memory address flipping to determine data content integrity in GPU sub-system

A graphics processing unit (GPU) of a GPU subsystem of a computing device processes graphics data to produce a plurality of portions of a first image, and to produce a plurality of portions of a second image. The GPU generates a plurality of data integrity check values associated with the plurality of portions of the first image, and a plurality of data integrity check values associated with the plurality of portions of the second image. The GPU determines whether each of the plurality of portions of the second image matches a corresponding portion of the first image. The GPU determines, prior to producing every portion of the second image, whether an operational fault has occurred in the GPU subsystem based at least in part the determination of whether each of the plurality of portions of the second image matches a corresponding portion of the first image.

Tile-based check values for data content integrity in a GPU subsystem

A method and manufacture for graphics processing in which a first line of raw Bayer data and a second line of raw Bayer data are received. Each two-by-two array of a plurality of non-overlapping two-by-two arrays of the first line of raw Bayer data and the second line of raw Bayer data is mapped as a separate corresponding texel to provide a plurality of texel. At least one operation is performed on at least one of the plurality of texels.

Graphics processing unit with bayer mapping

Natural-scene light is polarized so the light exiting the polarizer and entering a glass assembly has a first polarization. Light having a second polarization substantially orthogonal to the first polarization is launched into the glass assembly and directed normal to the glass assembly and into a zone plate assembly, along with the natural-scene light. A first plurality of electric fields is established in the zone assembly to form at least one zone plate that modulates the launched light without modulating the natural-scene light. The first plurality of electric fields is disestablished and a second plurality of electric fields is established in the zone plate assembly to reposition the at least one zone plate in the liquid crystal plate. Disestablishment and establishment of electric fields is repeated at a sufficient rate so that an image defined by a number of pixel spots formed on a retina is perceived by a viewer.

Optics display system with dynamic zone plate capability

A method, an apparatus, and a computer program product for modulating optics in a display are provided. An apparatus forms a plurality of zone plates in a liquid crystal using electric fields. Each zone plate has a center, and the centers are aligned along a first axis of the display. The apparatus moves the plurality of zone plates in a first direction along a second axis of the display different from the first axis of the display, while maintaining alignment of the centers of the plurality of zone plates along the first axis. Such movement is provided through repositioning of electric fields through the liquid crystal.

Dynamic zone plate augmented vision eyeglasses

A texture pipe of a graphics processing unit (GPU) may receive a texture data. The texture pipe may perform a block-based operation on the texture data, wherein the texture data comprises one or more blocks of texels. Shader processors of the GPU may process graphics data concurrently with the texture pipe performing the block-based operation. The texture pipe may output a result of performing the block-based operation on the one or more texture data.

Texture pipe as an image processing engine

An example method of filtering in a graphics processing unit (GPU) may include storing, by a texture engine of the GPU, filter coefficients of a filter as a texture memory object (TMO) in a texture cache of the GPU in response to a first instruction. The method may include retrieving, by the texture engine, filter coefficients from the texture cache in response to a second instruction. The method may include storing, by the texture engine, pixel data in the texture cache of the GPU in response to the second instruction. The pixel data may include one or more pixel values. The method may include filtering, by the texture engine, the pixel data stored in the texture cache using the retrieved filter coefficients.

Indefinite texture filter size for graphics processing

The techniques described in this disclosure are directed to validating an application that is to be executed on a graphics processing unit (GPU). For example, a validation server device may receive code of the application. The validation server device may provide some level of assurance that the application satisfies one or more performance criteria. In this manner, the probability of a problematic application executing on the device that includes the GPU may be reduced.

Validation of applications for graphics processing unit

This disclosure describes techniques for removing vertex points during two-dimensional (2D) graphics rendering using three-dimensional (3D) graphics hardware. In accordance with the described techniques one or more vertex points may be removed during 2D graphics rendering using 3D graphics hardware. For example, the techniques may remove redundant vertex points in the display coordinate space by discarding vertex points that have the substantially same positional coordinates in the display coordinate space as a previous vertex point. Alternatively or additionally, the techniques may remove excess vertex points that lie in a straight line. Removing the redundant vertex points or vertex points that lie in a straight line allow for more efficient utilization of the hardware resources of the GPU and increase the speed at which the GPU renders the image for display.

Discarding of vertex points during two-dimensional graphics rendering using three-dimensional graphics hardware

Techniques for supporting both 2-D and 3-D graphics are described. A graphics processing unit (GPU) may perform 3-D graphics processing in accordance with a 3-D graphics pipeline to render 3-D images and may also perform 2-D graphics processing in accordance with a 2-D graphics pipeline to render 2-D images. Each stage of the 2-D graphics pipeline may be mapped to at least one stage of the 3-D graphics pipeline. For example, a clipping, masking and scissoring stage in 2-D graphics may be mapped to a depth test stage in 3-D graphics. Coverage values for pixels within paths in 2-D graphics may be determined using rasterization and depth test stages in 3-D graphics. A paint generation stage and an image interpolation stage in 2-D graphics may be mapped to a fragment shader stage in 3-D graphics. A blending stage in 2-D graphics may be mapped to a blending stage in 3-D graphics.

Efficient 2-D and 3-D graphics processing

A computer addressing mode and memory access method rely on a memory segment identifier and a memory segment mask for indicating memory locations. In this addressing mode, a processor receives an instruction comprising the memory segment identifier and memory segment mask. The processor employs a two-level address decoding scheme to access individual memory locations. Under this decoding scheme, the processor decodes the memory segment identifier to select a particular memory segment. Each memory segment includes a predefined number of memory locations. The processor selects memory locations within the memory segment based on mask bits set in the memory segment mask. The disclosed addressing mode is advantageous because it allows non-consecutive memory locations to be efficiently accessed.

Growing community of inventors

Carlsbad, CA, United States of America

Jay Chunsup Yun