Texas Instruments Corporation

Jay Bryan Reimer

Patrick J Smith

Tai Huu Nguyen

Harland Glenn Hopkins

Kevin A McGonagle

Yi Luo

Charles Lance Fuoco

Brian Jason Karguth

Samuel Paul Visalli

Henry Nguyen

Duy Q Nguyen

Ramesh A Iyer

Dan K Bui

Natarajan Kurian Seshan

Jason A T Jones

Jason A Jones

Kun-Shan Lin

Martin Yu Li

H Glenn Hopkins

Irvinderpal S Ghai

Kenneth C Kelly

Shakuntala Anjanaiah

Robert D Doiron

Katsunobu Hirakawa

Weifeng Joe Zhou

A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.

Testing of fault detection circuit

A slave interface unit controls the exchange of data between a master processing unit and a plurality of slave processing units operating in the asynchronous transfer mode (ATM) of operation. The ATM slave interface unit has a receive unit and a transmit unit that exchange data cells and control signals with the ATM master processing unit. The receive unit and the transmit unit are coupled to a receive buffer storage unit and a transmit buffer storage unit, respectively. The receive buffer storage unit and the transmit buffer storage unit exchange data and control signals with the direct memory access unit. The ATM slave interface unit includes a configuration interface unit having a register that identifies the location in the data cell where the destination address is located and relates the destination address to the particular processing unit or memory location. The receive buffer unit uses the information in the register to determine the destination of the data cell.

Apparatus and method for an interface unit for data transfer between a host processing unit and a multi-target digital signal processing unit in an asynchronous transfer mode

A processing system comprises a digital signal processor (DSP) device and a host system on which the DSP device is implemented. The DSP device comprises a shared program memory and a plurality of processor subsystems coupled to the shared program memory to concurrently execute program instructions stored in the shared program memory. The host system is capable of independently debugging each subsystem. During debugging, the host device inserts breakpoints into the shared program memory and tracks the debug breakpoints to determine which subsystems are associated with the breakpoints. When a subsystem executes a breakpoint associated with that subsystem, the subsystem halts until the host gathers necessary debug information from the subsystem. However, when a subsystem executes a breakpoint that is not associated with that subsystem, the host system causes the subsystem to execute the original program instructions and proceed as directed.

Debugger breakpoint management in a multicore DSP device having shared program memory

In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. Using a first interrupt signal after each transfer of signal groups from the peripheral direct memory access unit, the data can be efficiently transferred from a channel memory of the peripheral direct memory access unit to the high level data link controller. A second interrupt from the high level data link controller when a last word of a packet is transferred thereto causes a new channel memory to be accessed. An abort signal is generated when a signal group for a packet being processed by the high level data link controller is not available in a timely manner.

Apparatus and method for responding to a interruption of a packet flow to a high level data link controller in a signal processing system

A digital signal processing system includes multiple processor subsystems, an external input/output port (XPORT), and an XPORT arbiter. The processor subsystems each include a processor core and a DMA controller. The XPORT arbiter arbitrates between the processor cores and between the DMA controllers, and further arbitrates between processor control or DMA control of the XPORT. Upon a request signal from a DMA controller, the XPORT arbiter asserts a hold signal to the processor cores. The processor cores respond by asserting a hold acknowledge signal. A processor core will delay the hold acknowledge signal until through with the XPORT. The arbiter, then asserts a grant signal to the DMA controller requesting access. The arbiter may assert a grant signal to a processor core requesting access. However, the processor core's access will be stalled as long as the hold signal is asserted.

External bus arbitration technique for multicore DSP device

A data processor timer comprising a writeable control register, a look-up table and a loadable counter. The loadable counter operates in a first mode to load the count data field and operates in a second mode an entry from said look-up table specified by the count data field. The loadable counter generating a time out signal upon counting a number of clock pulses equal to said count. The writeable control register preferably includes a mode bit selecting the first or second modes. This invention is suitable for a pre-scalar counter as part of a data processor watchdog timer.

Extended dynamic range watchdog timer

A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal processor includes a shared program memory, an emulation logic module, and multiple processor cores each coupled to the shared program memory by corresponding instruction buses. The emulation logic module preferably determines the operating modes of each of the processors, e.g., whether they are operating in a normal mode or an emulation mode. In the emulation mode, the emulation logic can alter the states of various processor hardware and the contents of various registers and memory. The instruction buses each include a read/write signal that, while their corresponding processor cores are in normal mode, is maintained in a read state. On the other hand, when the processor cores are in the emulation mode, the processor cores are allowed to determine the state of the instruction bus read/write signals. Each instruction bus read/write signal is preferably generated by a logic gate that prevents the processor core from affecting the read/write signal value in normal mode, but allows the processor core to determine the read/write signal value in emulation mode. In this manner, the logic gate prevents write operations to the shared program memory when the emulation logic de-asserts a signal indicative of emulation mode, and allows write operations to the shared program memory when the emulation logic asserts the signal indicative of emulation mode. The logic gate is preferably included in a bus interface module in each processor core.

Multicore DSP device having shared program memory with conditional write protection

A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.

Multicore DSP device having coupled subsystem memory buses for global DMA access

In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem. In response to a predetermined condition, the signal groups are forwarded to the identified digital signal processor subsystem. The channel block unit, in response to preselected signal groups, can direct the packet to a digital signal processor subsystem that is different from the digital signal processor subsystem identified by the address signal group.

Apparatus and method for distribution of signals from a high level data link controller to multiple digital signal processor cores

A multi-core DSP device includes a shared program memory to eliminate redundancy and thereby reduce the size and power consumption of the DSP device. Because each of the program cores typically executes the same software program, memory requirements may be reduced by having multiple processor cores share only a single copy of the software. Accordingly, a program memory couples to each of the processor cores by a corresponding instruction bus. Preferably the program memory services two or more instruction requests in each clock cycle. Data is preferably stored in separate memory arrays local to the processor core subsystems and accessible by the processor cores via a dedicated data bus. In one specific implementation, the program memory includes a wrapper that can perform one memory access in the first half of each clock cycle and a second memory access in the second half of each clock cycle. A designated set of instruction buses is allowed to arbitrate for only the first access, and the remaining instruction buses are allowed to arbitrate for only the second access. In this manner, a reduction in on-board memory requirements and associated power consumption may be advantageously reduced.

Shared program memory for use in multicore DSP devices

The present invention is a speech encoding technique useful in low data rate speech. Spoken input is analyzed to determine its basic phonological linguistic units and syllables. The pitch track for each syllable is compared with each of a predetermined set of pitch patterns. A pitch pattern forming the best match to the actual pitch track is selected for each syllable. Phonological linguistic unit indicia and pitch pattern indicia are transmitted to a speech synthesis apparatus. This synthesis apparatus matches the pitch pattern indicia to syllable groupings of the phonological linguistic unit indicia. During speech synthesis, sounds are produced corresponding to the phonological linguistic unit indicia with their primary pitch controlled by the pitch pattern indicia of the corresponding syllable. This achieves some measure of approximation to the primary pitch of the original spoken input at a low data rate. In the preferred embodiment, each pitch pattern includes an initial pitch slope, which may be zero indicating no change in pitch, a final pitch slope and a turning point between these two slopes.

Low data rate speech encoding employing syllable pitch patterns

A voice control system for controlling execution of a computer program includes a microphone (10) operative to receive voice commands having the output thereof connected to a clipping circuit (12) which amplifies and clips the microphone output to generate a zero-crossing signal. The output of circuit (12) is connected to a microprocessor (14) which on detecting speech input interrupts program execution in a CPU (15) and 'freezes' display device (16) on which the game is displayed. Microprocessor (14) then processes the input signal to recognize the voice command by determining the relative frequency content of discrete portions of the command. Once it has recognized the command, microprocessor (14) prompts the CPU (15) to execute the command and resume execution of the game program at the point of interrupt. By suspending the progress of the game during the speech input and recognition interval, the voice control system minimizes the time-constraint problems associated with voice input.

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Houston, TX, United States of America

Jay Bryan Reimer