Mitsubishi Electric Research Laboratories, Inc.

Mitsubishi Electric Information Technology Center America, Inc (ita)

Mitsubishi Electric Information Technology Center America, Inc.

Jay Bao

Tommy C Poon

Huifang Sun

Jyhchau Horng

Hiroyuki Nakayama

Yoshiki Mizutani

Anthony Vetro

Hisashi Kobayashi

Philip Orlik

Daqing Gu

Xiaoyang Lee

Pei Chen

Cheng-Youn Lu

Parthapratim De

Victor Sinyansky

Duanyi Wang

Shiyu Zeng

In orthogonal frequency division multiplexing systems, iterative maximum likelihood channel estimation and signal detection is preformed. The channel estimation gives the maximum likelihood estimates of time domain channel parameters. A cost function is defined. An iterative process estimates a joint channel impulse response and a transmitted signal that minimize the cost function, and thus solves the channel estimation and signal detection problem jointly without having specific knowledge of the channel.

Iterative maximum likelihood channel estimation and signal detection for OFDM systems

A wireless mobile communication network allows mobile, nodes, such as cellular telephone, and other types of mobile transceivers, to communicate with a fixed base station and directly with one another. This mobile to mobile communication capability is exploited through the formation of a local link where nodes with excess processing and bandwidth capacity forward messages at the request of the base station. The formation of the local link is adaptive and does not require a central controller. The wireless mobile network includes a base station and mobile nodes. Nodes are configured as a major nodes when they communicate information directly with the base station via a network link. Nodes are configured as minor nodes when they communicate the information indirectly with the base station via a direct local link with one of the major nodes to form a locally linked mobile network within the wireless mobile communications network. Each mobile node includes a header detector, coupled to a receiver and a decoder of the node to detect a header in a frame used to communicate the information, and a message processor, coupled to the header detector and a transmitter, to route the frame to the minor node.

Wireless mobile network with an adaptive locally linked mobile network for locally routing multimedia content

A digital video format converter and method therefor includes a first and second converter. The first converter receives a digital video signal and converts, in the frequency domain, inter-coded pictures in the digital video signal into intra-coded pictures. The first converter performs motion compensation in the frequency domain on the inter-coded pictures in the digital video signal to convert the inter-coded pictures into intra-coded pictures. The second converter down converts output of the first converter. Further signal processing then completes placing the digital video signal output by the second converter in a format acceptable to standard lower definition digital decoders.

Digital video format converter and method therefor

A digital receiver detects symbols in a baseband signal in a DS-CDMA network. The receiver includes multiple spaced apart antennas. A time-frequency rake receiver is connected to each of the antennas. An interference canceller is connected to each output of each of the rake receiver. Each interference canceller produces a contributing symbol in parallel. A diversity combiner determines a decision symbol corresponding to the baseband signal from the contributing symbols.

Adaptive DS-CDMA multi-user receiver with diversity combining for interference cancellation

A method reduces interference adaptively in a CDMA receiver. A baseband signal is demodulated to determine target symbols. The baseband signal is also demodulated to estimate interfering symbols. The interfering symbols are modulated to generate a cancellation signal, and the cancellation signal is subtracted from the base band signal to reduce interference in the target symbols.

Adaptive multi-users interference reduction and cancellation in a CDMA network

A digital transceiver system includes a downlink channel and an uplink channel. In the system, a transmitter transmits signals on the downlink channel and receives signals on the uplink channel. The transmitter includes a pre-coder having a plurality of filters. Each filter has a corresponding filter coefficient. The transmitter also includes a filter coefficient updater coupled to the pre-coder. A receiver of the system receives signals on the downlink channel and transmits signals on the uplink channel. The receiver includes linear equalizers having a plurality of taps. Each tap has a corresponding tap coefficient. The coefficient updater is configured to dynamically update the filter coefficients according to the tap coefficients which are indicative of the frequency response of the receiver.

Digital transceiver system with adaptive channel pre-coding in an asymmetrical communications network

A signal having one of a plurality of modulation formats is formed by encoding first data in accordance with a particular one of the modulation formats. The encoded first data is then combined with second data identifying the particular modulation format of the encoded first data to form the signal.

Generating signals having different modulation formats

In a digital radio receiver, transmitted symbols are recovered from a received signal that includes tim-shifted and frequency-shifted copies of a transmitted signal. A channel estimator extracts channel characteristics from a training signal. Receiver data and software for executing in a processor are stored in a memory connected to the processor. A parameter controller generates receiver configuration parameters from the channel characteristics and the receiver data. The received signal is decomposed into a matrix of samples according to the receiver configuration parameters to adapt the receiver to a multiple multiplexing schemes. An inner product is formed of the samples and channel characteristics, and the transmitted symbols are recovered from the inner product.

Software-based digital receiver adaptable to multiple multiplexing schemes

A matrix transform method and circuit provides for MAP decoding of turbo codes. The method begins by initializing a forward recursion probability function vector &agr; , and a backward recursion probability function vector &bgr; . Then, transition probability matrices &Ggr;(R ) and &Ggr; (R ) are determined according to each received symbol of the sequence R . And then, values of &agr; , corresponding to the received R are determined according to &Ggr;(R ). At the same time of determining &agr; , a plurality of multiplacation on &Ggr;(R ) and &Ggr; (R ) are accomplished in parallel. By making use of the results of the matrix multiplications, after receiving the complete symbol sequence R , values of all of the backward recursion probability vector &bgr; , where k&equals;1, 2, . . . , N&minus;1, are determined in parallel, and the log likelihood ratio for every decoded bit d , k&equals;1, 2, . . . , N, are also determined in parallel. The circuit performs successive decoding procedures in parallel using a set of regular matrix operations. These operations substantially accelerate the decoding speed and reduce the computational complexity, and are particularly suited for implementation in special-purpose parallel processing VLSI hardware architectures. Using shift registers, the VLSI implementation effectively reduces memory requirements and simplifies complicated data accesses and transfers.

MAP decoding for turbo codes by parallel matrix processing

A phase-lock loop circuit in a demodulator includes a timing recovery block and a carrier recovery block. The demodulator for demodulates a digital signal including symbols. The phase-lock loop includes an integrator processing a block of N samples to produce an average of the N symbols, and means for supplying the average of the N symbols to the timing recovery block and the carrier recovery block every NT period, where T is a sample time interval.

Programmable digital signal processor for demodulating digital television signals

An apparatus receives and demodulates digital signals encoded in multiple formats. The apparatus includes multiple processor units and a memory embedded with the processor units, and a cache connected to each of the processor units. The cache for communicating between the plurality of processors. The embedded memory can include data and instruction memory. The processor units and memory are configured as a multi-mode receiver demodulator front-end capable of receiving digitally modulated signals in multiple formats, and demodulating the signals in real-time in response any one of the multiple formats.

Embedded RAM based digital signal processor

In a receiver, an adaptive decision feedback equalizer receives broadcast signals having multipath interference. The equalizer includes a feed-forward, a feedback, and a partial feedback forward filter. The equalizer also includes a slicer and two accumulators. An output from the slicer is processed by the feedback filter and the partial feedback filter. The output from the feedback filter is subtracted from output of the feed-forward filter to form the input to the slicer, and the output of the partial feedback filter is subtracted from the received signal to form the input for the feed-forward filter to reduce the multipath interference.

Method and apparatus for equalizing a digital signal received via multiple transmission paths

An antenna is directed to optimally receive an advanced television signal. First, the strength of the signal is measured as a function of the azimuth angle of the antenna, and second the flatness of the signal is measured as a function of the azimuth angle of the antenna. The antenna is then rotated to maximize the flatness of the signal while maintaining the strength of the signal above a minimum threshold.

Directing an antenna to receive digital television signals

An apparatus for processing digital signals includes a multiplier having a first input and a second input and an output producing a product. An adder is connected to receive the product from the multiplier as a first input to produce a sum. A first register is connected to receive and store the sum and to provide a second input to the adder in response to a clock signal. A second register is connected to receive and store the output of the first register in response to an inverse of the clock signal to enable the addition of two products in a single clock cycle.

Multiple function processing core for communication signals

A universal modem has a software-configurable modulator/demodulator which accommodates different modulation formats such as those associated with terrestrial, cable, phone line, satellite and wireless communications to be transmitted and received through a single device in which the modem has reconfigurable logic to accommodate the format of the signals being received or transmitted. In one embodiment, the system tracks channel noise and changes modulation format at both the transmit and receive sides of the system through the use of a controller that controls both sides.

Growing community of inventors

Bridgewater, NJ, United States of America

Jay Bao