Intel Corporation

Jay B Miller

Lawrence T Clark

Mark A Schaecher

Richard J Burgess, Jr

A write circuit structure may be used to transfer data between global bit lines and local bit lines of a cache. The write circuit structure located between the hierarchical bit lines may be buffers in parallel with P-channel devices in one embodiment or cross-coupled P-channel and N-channel devices in another embodiment.

Cross-coupled write circuit

A processor having an L1 cache memory that may use a compare circuit to determine matches of stored tag information against an address and gate sense amps of the cache memory with a cache-hit signal.

Low power set associative cache

In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to drive the first plurality of CAM cells. The first plurality of CAM drivers prevent the first plurality of CAM cells from participating in a match when the array is in a test mode.

Method and apparatus for testing a CAM addressed cache

A method for conserving power during a cache memory operation is disclosed. The validity and the parity of the tag address are checked. If the tag is invalid or the parity bit does not check, the tag is not read and a tag comparison is not performed, such that the data is accessed from the main memory. Otherwise, the tag address bits are selected in a plurality of tag subsets. A first tag subset of the plurality of tag subsets is compared with a respective first subset of the tag field of the memory address bits. A first compare signal indicative of the result of the first comparison is outputted. The cache memory operation is interrupted if the first compare signal indicates the first tag subset does not match the respective first subset of the tag field of the memory address.

Low power cache operation through the use of partial tag comparison

A method and apparatus for improving the access time of a memory device is described. The location based timing scheme utilizes a subset of the address bits to adjust the timing of the sense amplifier enable in order to achieve a faster read of the information stored in the memory cell.

Growing community of inventors

Chandler, AZ, United States of America

Jay B Miller