Apple Inc.

Jay B Fletcher

Shawn Searles

Sanjay Pant

Fabio Gozzini

Nathan F Hanagami

Hao Zhou

Sujan K Manohar

Hubert Attah

Dingkun Du

Vincent R Von Kaenel

Bo Yang

Floyd L Dankert

Nir Dahan

Olivier Girard

Ruopeng Wang

Karthik Manickam

Victor Zyuban

Michael B Nussbaum

Talbott Mead Houk

Mark A Yoshimoto

Dashun Xue

Vincenzo Bisogno

Siarhei Meliukh

Erick Omar Torres

Nikola Jovanovic

Di Zhao

Wenxun Huang

Alessandro Molari

Enrico Zanetti

Jitendra K Agrawal

Sarfraz Shaikh

Chongli Cai

Ludmil N Nikolov

Hartmut Sturm

Tiago Filipe Galhoz Patrao

Seyedeh Maryam Mortazavi Zanjani

Tristan R Hudson

Chad L Olson

John J Sullivan

Nicola Florio

Michael P Wigley

Mircea-Andrei Lazar

Jonathan A Dutra

Jiandong Jiang

The present disclosure describes a system with a power management device, a wakeup circuit, a battery management device, and a connector. During a powered down mode of operation, the battery management device can provide, via the connector, a bias voltage to the wakeup circuit. In response to a wakeup switch being activated, the battery management device can provide a power supply (e.g., from a battery) to the power management device. Benefits of the wakeup circuit include (1) a reduction of battery consumption—and thus improving battery lifetime—when the electronic system is in a powered down mode of operation because the wakeup circuit has lower number of active components compared to other designs and (2) a non-complex wakeup circuit design because one or more existing connector interconnects between the power management device and the battery management device can be re-used during electronic system's powered down mode of operation.

Wakeup circuit

In some embodiments, a power converter circuit included in a computer system magnetizes and de-magnetizes an inductor coupled to a switch node using high-side and low-side switches to alternatively couple a switch node to an input power supply node and a ground supply node. In response to detecting a drop in the voltage level of the input power supply node, the power converter circuit may adjust an on-resistance of the high-side switch to maintain performance at the lower voltage level of the input power supply node.

Power converter with overdrive switch control

A power management circuit for computer systems includes a power converter circuit that generates different voltage levels at different time periods. Multiple voltage regulator circuits are coupled to the output of the power converter circuit and to respective local power supply nodes. Switch devices are used to bypass the voltage regulator circuits during corresponding ones of the different time periods.

Power converter circuit for use with multiple low-current power rails

A regulator circuit included in a computer system may include a control circuit and multiple pass circuits that source respective supply currents to a regulated power supply node by adjusting respective conductance values between an input power supply node and the regulated power supply node. The number of pass circuits can be adjusted on a design-by-design basis based on a threshold load current for the regulator circuit or on a threshold conductance between the input power supply node and the regulated power supply node. The control circuit adjusts the respective conductance values using a combination of respective sense currents generated by the multiple pass circuits along with a reference voltage and a voltage level of the regulated power supply node.

Scalable low dropout regulator having multiple pass circuits

A voltage regulator circuit included in a computer system may employ a control circuit and a switch array that includes multiple switch circuits. Different groups of switch circuits that include respective groups of switch devices are coupled between an input power supply node and corresponding regulated power supply nodes. To maintain desired respective voltages on the regulated power supply nodes, the control circuit compares the voltages of the regulated power supply nodes to corresponding reference voltages and, based on results of the comparisons, opens and closes various ones of the switch devices included in the different groups of switch circuits.

Regulator switch array

A power converter circuit included in a computer system magnetizes and de-magnetizes an inductor coupled to a switch node using high-side and low-side switches to alternatively couple a switch node to an input power supply node and a ground supply node. In response to detecting a drop in the voltage level of the input power supply node, the power converter circuit may adjust an on-resistance of the high-side switch to maintain performance at the lower voltage level of the input power supply node.

A voltage regulator having a multi-level, multi-phase architecture is disclosed. The circuit includes a two-level buck converter and an N-level buck converter each coupled to an output node, wherein N is an integer value of three or more. During operation, the two-level buck converter provides one of two possible voltages to a first inductor. The N-level buck converter provides, during operation, one of N voltages to a second inductor. The first and second inductors each convert respectively received voltages to currents, which are provided to a common output node. A control circuit controls the activation of transistors in each of the two-level and N-level buck converters in such a manner as to cause the voltage on the output node to be maintained at a desired level.

Voltage regulator with multi-level, multi-phase buck architecture

A power converter circuit that includes multiple phase circuits may employ coupled inductors to generate a particular voltage level on a regulated power supply node. Based on a comparison of a voltage level of the regulated power supply node and a reference voltage, the power converter circuit may initiate an active period, during which the phase circuits source respective currents to the regulated power supply node via corresponding coils included in the coupled inductor. After a time period has elapsed following an initiation of the active period, the operation of the phase circuits is adjusted so that the respective currents flowing in the coils of the coupled inductor are out of phase.

Pulse frequency modulation control methods for multi-phase power converters with coupled inductors

A voltage regulator circuit included in a computer system may generate a voltage level on a power supply signal using a source power supply signal and based initial values of one or more operation parameters derived from wafer-level test data. One or more operation characteristics of the voltage regulator circuit may be sampled, by a measurement circuit, at multiple time points to generated measurement data. A control circuit may adapt operation of the voltage regulator circuit based on the measurement data.

Computer system power monitoring

A power management circuit included in a computer system regulates a voltage level of a power supply node used by other circuits in the computer system. The power management circuit includes a control circuit and multiple phase circuits coupled to the regulated power supply node via corresponding inductors. The control circuit selectively activates particular ones of the multiple phase circuits allowing them source respective currents to the regulated power supply node. The control circuit also selectively activates particular ones of other phase circuits that are external to the power management circuit and coupled to the regulated power supply node via their own corresponding inductors. Once activated, the external phase circuits source respective currents to the regulated power supply node via their corresponding inductors.

Multi-phase power converter with external phase circuits

A voltage regulator circuit includes a switch device that is coupled between an input power supply and a regulated power supply node. The voltage regulator circuit adjusts a value of a current flowing from the input power supply to the regulated power supply node by modifying a voltage level of a control node coupled to the switch device. A control circuit adjusts the voltage level of the control node using an error signal based on a comparison of the voltage level of the regulated power supply node and a reference voltage. To improve the response time of the voltage regulator circuit to changes in load current, the control circuit additionally sources current to and/or sinks current from the control node based on a voltage level of the control node.

Voltage mode low-dropout regulator circuit with reduced quiescent current

A dropout detection circuit for an LDO voltage regulator is disclosed. An LDO voltage regulator includes a power transistor having a drain terminal coupled to an output voltage node and a gate terminal coupled to an output of an error amplifier. A source terminal of the power transistor is coupled to an input voltage node. The circuit further includes a detection circuit having a first input coupled to the gate terminal and a second input coupled to the drain terminal. The detection circuit is configured to generate an indication responsive to detecting that the LDO voltage regulator has entered operation below a minimum dropout.

Voltage regulator dropout detection

A voltage regulator circuit included in a computer system may include multiple devices and a switch node coupled to a regulated power supply node via an inductor. The voltage regulator circuit may charge a capacitor using an input power supply signal, and couple the capacitor to the switch node using respective subsets of the multiple devices, which are selected based on one or more control signals. A control circuit may generate the one or more control signals based on a particular switching sequence, which is selected based on a ratio of a voltage level of the regulated power supply node and a voltage level input power supply signal.

Cycle transitions for buck converter circuits

A dual loop LDO voltage regulator is disclosed. The voltage regulator circuit includes a first current mirror having first and second transistors having source terminals coupled to an input voltage node. The circuit further includes a second current mirror having third and fourth transistors, wherein drain terminals of the third and fourth transistors are coupled to drain terminals of the first and second transistors, respectively. A feedback circuit is coupled between source terminals of the third and fourth transistors, and is configured to generate a feedback signal based on a reference voltage and an output voltage present on the source terminal of the fourth transistor. The first and second current mirrors form a first control loop, and wherein the first and second current mirrors and the feedback circuit form a second control loop.

Dual loop LDO voltage regulator

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Austin, TX, United States of America

Jay B Fletcher