Visual Information Technologies, Inc.

Other

Jay A Thompson

Michael K Corry

David T Stoner

John P Norsworthy

David M Pfeiffer

James A Fontaine

Dwight D Dipert

A system and method of selectively connecting at least two articles of clothing is provided. First and second articles, which may comprise a glove and jacket sleeve or cuff, have mating geometries and at least one fastener to securely and selectively connect the two articles. In certain embodiments, magnets are provided as fasteners to connect the articles. For example, in certain embodiments, a method and system is provided that comprises features adapted to allow connection of an accessory (e.g. ski glove) to a portion of another article (e.g. jacket).

System and method for connecting garments and related articles

A system and method for illuminating an area proximate a trailer, such as a boat or snowmobile trailer. At least one area illuminating light is connected to an area illuminating lighting control member. The area illuminating lighting control member receives and interprets trailer lighting control signals for determining when to activate and deactivate the area illuminating light. Control signals include is a trailer tow vehicle 'lights on' condition combined with a second trailer lighting control signal, such as a 'reverse lights on' indication, or indications from a water sensor or manual switch. The area illuminating lighting control member also receives a set of trailer lighting control signals for automatically deactivating the trailer illuminating lighting, including a 'running light off' indication, a 'brake lights on' indication, and/or a 'turn signal lights on' indication. The trailer includes trailer lighting, which may optionally be deactivated by a disabling signal from the area illuminating lighting control member based on input from a sensor such as a water sensor.

Automatic trailer illuminating lighting control system

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). A window clipping circuitry monitors the memory addresses from the image algorithm processor (66) to determined whether one or more pixels of a multi-pixel word are located outside of a window.

High speed image processing computer with overlapping windows-div

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) assocated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). Mask data is generated by a mask processor coupled to the image algorithm processor (66) for masking one or more pixels in a multi-pixel word and further for masking individual bits within said pixels.

High speed image processing computer

Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). The overlay processor is operable to generate page addresses to the color look-up tables responsive to image data in the overlay memory plane.

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116).

High speed image processing system using separate data processor and

Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). An error correction circuit is operable to detect and correct faulty data transferred between the image memory planes and their respective data processors.

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Plano, TX, United States of America

Jay A Thompson