Fairchild Camera and Instrument Corp.

Other

Jay A Shideler

Umeshwar D Mishra

Robert L Berry

An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to the collector of the vertical NPN through a buried contact region accessed through a sink region formed in an adjacent island of semiconductor material. A field implantation beneath the isolation oxide avoids implanting impurity along the sidewalls of the semiconductor material adjacent the field oxidation and therefore provides both vertical and lateral isolation from one silicon island to another. Substantial reductions in sink sizes and cell sizes are obtained by eliminating the field diffusions from the sidewalls of the semiconductor islands. The lateral PNP transistor serves as an active load for a memory circuit constructed using the structure of this invention. The process also can be used to manufacture PROMs from vertical NPN transistors. An LV.sub.CEO implant is used to increase the breakdown voltage of each vertical transistor from its collector-to-emitter thereby allowing junction avalanching of selected emitter-base junctions to program selected PROMs in the array even though the programming voltage is only a few volts beneath the breakdown voltage of the oxide isolated structure.

Junction programmable vertical transistor with high performance

An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to the collector of the vertical NPN through a buried contact region accessed through a sink region formed in an adjacent island of semiconductor material. A field implantation beneath the isolation oxide avoids implanting impurity along the sidewalls of the semiconductor material adjacent the field oxidation and therefore provides both vertical and lateral isolation from one silicon island to another. Substantial reductions in sink sizes and cell sizes are obtained by elminating the field diffusions from the sidewalls of the semiconductor islands. The lateral PNP transistor serves as an active load for a memory circuit constructed using the structure of this invention. The process also can be used to manufacutre PROMS from vertical NPN transistors. An LV.sub.CEO implant is used to increase the breakdown voltage of each vertical transistor from its collector-to-emitter thereby allowing junction avalanching of selected emitter-base junctions to program selected PROMs in the array even though the programming voltage is only a few volts beneath the breakdown voltage of the oxide isolated structure.

Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM

A lateral bipolar transistor having a base width of 0.5 micron or less is made by forming a protective layer on an electrically insulating layer along a surface of a semiconductor body, forming an open space through the protective layer so as to define a guiding edge for it, introducing a first semiconductor dopant of a selected conductivity type into the body using the guiding edge to control the lateral extent of the first dopant, etching the insulating layer back under the protective layer a selected distance from the guiding edge, oxidizing material of the body exposed by the open space in the protective and insulating layers to form a composite electrically insulating region, removing the remainder of the protective layer, etching the insulating region sufficiently long to create an open space through it and thereby define another guiding edge, and introducing a second semiconductor dopant of the selected conductivity type into the body using this second guiding edge to control the lateral extent of the second dopant toward the first dopant and thereby to control the resulting base width.

Growing community of inventors

San Mateo, CA, United States of America

Jay A Shideler