Motorola Corporation

Freescale Semiconductor,inc.

Jay A Hartvigsen

William C Moyer

Wallace B Harwood, Iii

Rand L Gray

John E Zolnowsky

John J Vaglica

James M Sibigtroth

James B Eifert

David S Mothersole

Robert R Thompson

Michael C Wood

Chinh H Le

Nigel J Allison

Jeffrey A Hopkins

David S Motersole

Russell C Stanphill

A debug module ( ) is provided which allows a developer to capture three types of debug information. The three types of debug information are: change-of-flow addresses, CPU data, and current instruction addresses. The debug information is captured in an on-chip debug FIFO memory ( ) during program development. The debug information is provided to an external host via a serial communication interface ( ) for post-processing and analysis. Storing and retrieving program information in this way is useful in microcontrollers that do not provide external access to address and data bus signals.

Data processing system with on-chip FIFO for storing debug information and method therefor

A method and apparatus for providing an external indication of internal cycles in a data processing system (10) in order to more easily debug software being executed by data processing system (10). In one embodiment, data processing system (10) provides cycle type signals (14) external to data processing system (10). The cycle type signals (14) can be used to determine a variety of information about the activity and bus cycles being performed within data processing system (10), activity which is not readily discernible except by way of the cycle type signals (14). In some cases the information provided by the cycle type signals (14) is sufficient for debug purposes; in other cases, information from additional signals, e.g. the address type signals (15) and the read/write signal (19) may also be required.

Method and apparatus for providing an external indication of internal

The present invention relates in general to a data processing system (10), and more particularly to a method and apparatus for controlling showcycles in a data processing system (10) to provide user control over the tradeoff between internal bus visibility and operating performance. In one embodiment, the functionality of one or more register control bits (100, 102) can be combined with the functionality of one or more externally provided signals (78) to allow the user to have a wide range of control over the show cycles provided on external bus 12. The user is thus able to continuously select and change which information is provided by way of show cycles on external bus 12. As a result, the difficulty of debugging software program code can potentially be reduced.

Method and apparatus for controlling show cycles in a data processing

A data processor with development support features includes an alternate mode of operation in which instructions are received by means of an externally-controlled path. The connections used by the externally-controlled path are not shared by any system resources accessible to the data processor in the normal mode of operation, but are used by other development support features in the normal mode. In a preferred embodiment, an integrated circuit microcomputer includes such a data processor as its CPU. The CPU has access to on-chip peripherals and memory, in addition to off-chip peripherals and memory, in both the normal and alternate modes of operation, by means of a parallel bus which it operates as a bus master. In the alternate mode, the CPU receives instructions by means of a serial bus on which the CPU is a slave device.

Data processor with development support features

A data processing system having a debug peripheral is provided. The debug peripheral is coupled to a central processing unit and memory via an internal communications bus. The debug peripheral is a single-word dual port memory with parallel read-write write access on one side, and synchronous, full-duplex serial read-write access on the other side. The serial side of the debug peripheral is connected to external emulation hardware by means of a three-pin synchronous serial interface. The parallel access is via a connection to a core central processing unit (CPU) internal communications bus. The debug peripheral is addressed at sixteen adjacent locations in the CPU memory space. During a debug interlude, the debug peripheral assumes control of the CPU by providing an interrup signal to the CPU, and thereby causing the CPU to fetch instructions directly from the debug peripheral. The debug peripheral receives instructions from the external emulation hardware, and provides the debug instructions to the CPU, in response to an instruction address provided by the CPU.

No-chip debug peripheral which uses externally provided instructions to

In a data processing system comprising a central processing unit (CPU), a memory management unit (MMU) and a storage system, the MMU translates each of the logical addresses output by the CPU to a corresponding physical address in the storage system by selectively using translation descriptors stored in an address translation cache. In response to receiving a dynamic disable signal, the MMU will provide each logical address as the corresponding physical address without translation. In addition, the MMU will preserve the state of the entries in the address translation cache, and 'freeze' the translation activities.

Dynamic disable mechanism for a memory management unit

A data processor is provided with status logic for monitoring the instruction processing activity therein, and for providing a pulse width encoded status output signal having either a first duration if the next instruction is to be executed in a normal sequence, or a second duration if an exception condition has occurred which will delay or prevent the execution of the next instruction. In the preferred form, the status logic can detect various types of exception conditions in the CPU and will assert the status signal for respective durations for each such type. In a data processor having an internal instruction pipeline, the status logic may also monitor changes in the flow of instructions, and provide a 'refill' signal to indicate that the prefetched instructions in the pipeline have be discarded.

Data processor having pulse width encoded status output signal

In a data processor adapted to perform operations upon operands of a given size, a bus controller is provided to communicate the operands with a storage device having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller requesting the transfer of an operand of a particular size, the storage device provides a size signal indicating the size of the data port available to accommodate the requested transfer. Depending upon the size of the operand to be transferred and the size of the data port of the storage device, the bus controller may break the operand transfer cycle into several bus cycles in order to completely transfer the operand. In the process, the bus controller compensates for any address misalignment between the operand and the data port. In order to distinguish individual operand cycles from the several bus cycles which may comprise the operand cycle, the bus controller provides an operand cycle start signal only at the start of the first bus cycle of each operand cycle.

Data processor having multiple cycle operand cycles

A data processor is adapted for operation with a memory containing a plurality of items of operating information for the data processor. In addition a cache stores a selected number of all of the items of the operating information. When the cache provides an item of operating information, the memory is not requested to provide the item so that a user of the data processor cannot detect the request for the item. A disable circuit is provided to prevent the cache from providing the item when a signal external to the data processor is provided. Consequently, a user, with the external signal, can cause the data processor to make all of its requests for items of operating information to the memory where these requests can be detected.

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Austin, TX, United States of America

Jay A Hartvigsen