Integrated Memory Logic, Inc.

Mosys, Inc.

Silicon Access Networks, Inc.

Jawji Chen

Kameswara K Rao

Shuen-Chin Chang

Yong E Park

Stephen Fung

J Eric Ruetz

Vithal Rao

Da-Guang Yu

Chee T Chua

Subramani Kengeri

Jeongsik Yang

Chiayao S Tung

Cindy Yuklin Ng

A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.

Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process

A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.

Two bits per cell non-volatile memory architecture

An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream

An advanced input/output interface is provided for an integrated circuit memory having a memory storage array accessible by signals formatted in a two-level protocol. The advanced input/output interface includes a bit compression circuit for receiving a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit memory. The bit compression circuit converts the first plurality of two-level protocol signals into a first signal formatted in a multi-level protocol. A bit decompression circuit receives a second signal formatted in the multi-level protocol. The bit decompression circuit converts the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol. In one embodiment, the advanced input/output interface allows for high speed/bandwidth memory accesses while reducing the pin count and operating frequency required for operation.

Advanced input/output interface for an integrated circuit device using two-level to multi-level signal conversion

A system and/or method for simultaneous read/write access of 1-Transistor (1-T) dynamic random access memory (DRAM), which does not rely on a dual-port DRAM to perform read and write accesses within single clock cycle. A single-port 1-T DRAM works with modified design of read sense amplifier to perform both read and write accesses within single clock cycle, thereby retaining high performance and compact size that characterize the 1-T DRAM while allowing simultaneous read/write access that characterizes dual-port memory. Hence, single-port 1-T DRAM constitutes a pseudo dual-port 1-T DRAM that emulates the dual-port DRAM's ability in performing simultaneous read/write memory access of 1-T DRAM.

Pseudo dual-port DRAM for simultaneous read/write access

In accordance with this invention, an arbitration unit controls access to a shared device between a plurality devices. The arbitration unit grants access to the shared device so that both the maximum latency requirement and the minimum access requirement of the devices are satisfied. In one embodiment, a first device with high access requirements uses the precedence of a second device when the second device has a higher precedence than the first device and the second device does not request access to the shared device. Thus the first device can receive access to the shared device based on the precedence of the second device or the precedence of the first device. In another embodiment, the devices are circularly ordered to determine the precedence of each device. In accordance with circular arbitration, after the first device receives access to the shared device based on the precedence of the second device, the second device is assigned the lowest precedence. Furthermore, some embodiments arrange the devices in a hierarchy of different groups. A first group within a second group is treated as a single device of the second group. One implementation of the arbitration unit includes a group pointer for each group and a precedence decoder.

Growing community of inventors

Fremont, CA, United States of America

Jawji Chen