International Business Machines Corporation

Jawahar P Nayak

John Ulrich Knickerbocker

David Clifford Long

Thomas M Shaw

Xiao Hu Liu

Conal Eugene Murray

Vincent James McGahay

Dinesh Gupta

Michael E Cropp

Steven H Voldman

Mark Alan Lavin

James A Culp

Werner A Rausch

Fook-Luen Heng

Lester W Herron

Rama Nand Singh

Hazara Singh Rathore

Robert Anthony Rita

Habib Hichri

Du Binh Nguyen

Birendra N Agarwala

Brenda Lee Peterson

Melanie J Sherony

Chieh-Yu Lin

Jin-Fuw Lee

Noah D Zamdmer

Conrad A Barile

John M Wargo

Nancy A Wier-Cavalieri

Charles W Hunter, Jr

Jon Alfred Casey

Hormazdyar M Dalal

Michael Wayne Lane

James N Humenik

Rao Venkateswara Vallabhaneni

Keith C O'Neil

Ernest N Levine

Renee L Weisman

John R Lankard, Jr

James C Utter

Gerald H Leino

Deborah Anne Sylvester

John A Trumpetto

L Wynn Herron

Richard J Cassidy

Brett H Engle

James M Blazick

John F McGrath

Frank V Ranalli

A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization.

System and method for employing patterning process statistics for ground rules waivers and optimization

Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

Building metal pillars in a chip for structure support

The present invention provides an interconnect structure that includes a diffusion barrier which is positioned within the structure in a fashion that increases the reliability and lifetime of the interconnect structure.

Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines

Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

Stacked via-stud with improved reliability in copper metallurgy

A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

Halo-free non-rectifying contact on chip with halo source/drain diffusion

A process wherein a low viscosity, metal-containing paste is screened onto a ceramic greensheet and then sets up to increase its viscosity. In one method, the low viscosity is caused by excess solvent which is then blotted or otherwise removed so that the viscosity of the paste is increased. In an alternative method, the low viscosity paste contains a cross-linking agent which causes the paste to increase its viscosity after screening.

Process for screening features on an electronic substrate with a low viscosity paste

A method and structure for personalizing a multi-layer substrate structure includes supplying a generic layer having electrical features and altering the electrical features to produce a personalized layer of the multi-layer substrate.

Pre-patterned substrate layers for being personalized as needed

A process of forming a multi-layer feature on a ceramic or organic article in which first and second layers of paste are sequentially screened through a screening mask wherein the screening mask has not been moved between screening steps. A structure produced by this process is also disclosed.

Single mask screening process

In the formation of multilayer ceramic substrates, greensheets are utilized which have the same pattern and number of vias punched in each greensheet. Then, selected vias may be filled with metallic paste to form the internal connections of the multilayer ceramic substrate. The remaining vias may be filled with a fugitive material or left totally unfilled. Also disclosed is the multilayer ceramic substrate produced by this method.

Method of forming a multilayer ceramic substrate with max-punched vias

Disclosed is a method for reducing screening defects on ceramic greensheets which includes placing additional vias in the kerf that will be eventually discarded during the sizing operation. Also disclosed is a ceramic substrate laminate article with reduced screening defects.

Defect reduction method for screened greensheets and article produced therefrom

Deformation of vias and shorting between vias during screening of conductive paste onto greensheets wider than 185 mm is avoided by a concentration of thixotropic agent in the conductive paste formulation to a concentration which raises the thixotropic index of the paste to within 5% to 25% of the maximum achievable thixotropic index for the organic vehicle in the paste. For a paste containing molybdenum powder in which the organic vehicle is a mixture of ethyl cellulose, texanol and oleoyl sarcosine, this criterion corresponds to a concentration of glycerl tri(-12-hydroxystearate) in the range of 1.4% to 1.8% by weight.

Conductive paste for large greensheet screening including high

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Wappingers Falls, NY, United States of America

Jawahar P Nayak