Intel Corporation

Shenzhen Chipuller Chip Technology Co., Ltd

Other

Zglue, Inc.

Jawad Nasrullah

David Pardo Keppel

Kelvin Kwan

James B Burr

Archisman Bagchi

David Roger Ditzel

Vjekoslav Svilan

Hao Hua

Omar Alnaggar

Hanfeng Wang

Mohamed Sameh Mahmoud

Muhammad M Khellah

Christopher B Wilkerson

Jaydeep P Kulkarni

Helia A Naeimi

Omar Mahmoud Afdal Alnaggar

Ming Zhang

Zhiquan Luo

Described is an apparatus for supporting Over-The-Air Hardware Updates comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to be fastened and electrically coupled in one or more regions to one or more respectively corresponding semiconductor dies. The second circuitry may be operable to configure the one or more regions of the first circuitry. The third circuitry may be operable to provide a set of wirelessly-received configuration instructions to the second circuitry.

Over-the-air hardware update

Described are methods and apparatuses pertaining to stacked integrated circuits having application in ultra-low-power and small form factor design, with fast prototyping and mass-production cycle time, including application for millimeter wave radio frequency circuits.

Method and apparatus to use active semiconductor interposers for RF signal chain in modular stacked integrated circuits

Described is a packaged component having a first surface and an opposite second surface. The packaged component may comprise a first element a second element, and a third element. The first element may have a first surface and an opposite second surface. The second element may have a first surface and an opposite second surface. The third element may electrically connect a portion of the first element to a portion of the second element. The second surface of the first element may be adjacent to the second surface of the packaged component, and the second surface of the second element may be adjacent to the second surface of the packaged component.

Assembly of flexible and integrated module packages with leadframes

Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.

Method and systems for energy efficiency and energy conservation including on-off keying for power control

In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.

Controlling processor consumption using on-off keying having a maxiumum off time

A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor.

Apparatus and method for flushing dirty cache lines based on cache activity levels

A system according to some examples herein includes a base chip which may include a plurality of attachment slots for attaching dies thereto. One or more of the attachment slots may be programmable attachment slots. The base chip may further include circuitry for interconnecting the dies attached to the base chip. For example, the base chip may include a plurality of cross bar switches, each of which is associated with respective ones of the plurality of attachment slots. The base chip may further include a configuration block, which is adapted to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and which is further adapted to receive configuration data for programming signal (including power and ground) channels of the cross bar switches.

System and methods for producing modular stacked integrated circuits

In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the on and off times vary depending on whether and when an interrupt is incurred. Other embodiments are described and claimed.

Controlling power consumption of a processor using interrupt-mediated on-off keying

Systems and methods for entry and exit latency reduction for low power states are described. In one embodiment, a computer implemented method initiates an energy-efficient low power state (e.g., deep sleep state) to reduce power consumption of a device. The method sets a power supply voltage that provides sufficient power to a dual power supply array for retention of states. Logic is powered down in this low power state.

Methods and systems for energy efficiency and energy conservation including entry and exit latency reduction for low power states

Apparatus and method for reduced core entry into a power state having a powered down core cache

Controlling processor consumption using on-off keying having a maximum off time

An apparatus and method for scrubbing spin transfer torque (STT) memory. For example, one embodiment of a apparatus comprises: a memory subsystem including at least one spin transfer torque (STT) memory, the STT memory arranged into one or more entries; and a scrub engine to ensure that the entries of the STT contain valid data, the scrub engine including analysis and processing logic to determine, for each entry, whether a specified scrubbing interval has expired and, if so, then to invalidate the entry or re-fetch data for the entry from a source and, if the scrubbing interval has not expired, then to perform error detection and/or correction on the entry.

Method and apparatus for managing a spin transfer torque memory

In one embodiment, a processor includes at least one sleep block and a central sleep controller. The at least one sleep block may include at least one execution unit, at least one processor component, and sleep logic. The central sleep controller may be to program the sleep logic to perform at least one sleep transition for the at least one sleep block, and to operate in a first sleep mode. The sleep logic may be to perform the at least one sleep transition for the at least one sleep block without waking the central sleep controller from the first sleep mode. Other embodiments are described and claimed.

Growing community of inventors

Palo Alto, CA, United States of America

Jawad Nasrullah