Stmicroelectronics (alps) Sas

Stmicroelectronics (grenoble 2) Sas

Stmicroelectronics International N.v.

Jawad Benhammadi

Sylvain Meyer

EEPROM emulation is provided in a phase-change memory of a circuit integrating a microprocessor. A granularity for writing into lines of the phase-change memory is defined according to a size of data packets to be written. A first error correction code calculated by a program executed by said microprocessor is associated with each data packet. Several data packets and their associated first error correction codes are then stored in a same line of the phase-change memory data packet.

EEPROM emulation method

A FLASH memory device includes a FLASH memory having an array of non-volatile memory cells and a volatile memory. A FLASH memory interface is arranged outside of the FLASH memory, and a first communication bus couples the FLASH memory interface to the array of memory cells. A second communication bus couples the FLASH memory interface to the volatile memory.

Flash memory device

In accordance with an embodiment, a method includes: performing a first write operation comprising writing a first data packet to a first portion of a first line of a flash memory; and performing a second write operation comprising writing a second data packet to a second portion of the first line of the flash memory, wherein the first line comprises the first data packet and the second data packet after performing the first write operation and the second write operation.

Data memory emulation in flash memory

In an embodiment a method includes modifying or suppressing one or more data values of a non-volatile memory, wherein the one or more data values are stored in a first sector of the non-volatile memory, wherein the first sector is designated as a current sector by one or more selection values stored in the non-volatile memory, wherein modifying or suppressing comprises writing the one or more data values into a second sector of the non-volatile memory, and wherein the second sector is designated as an alternate sector by the one or more selection values.

Method for managing a zone of sensitive data in a flash memory

The present description concerns a method comprising: the loading, from a non-volatile memory of a circuit to a computation circuit, of a first security parameter of the circuit and of a first error-correcting code stored in association with the first security parameter; the verification, by the computation circuit, of the first security parameter and of the first error-correcting code to determine whether one or a plurality of the bits of the security parameter are erroneous; and if it is determined that two bits of the security parameter are erroneous, the loading of a default value of the first parameter into a register.

Secure non-volatile memory

In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.

Interrupt controller and method of managing an interrupt controller

In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.

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Pont de Claix, France

Jawad Benhammadi