Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Other

Jawad Basit Khan

Sanjeev N Trika

Richard L Coulson

Peng T Li

Chetan Chauhan

Knut Stener Grimsrud

Sourabh Dongaonkar

Rajesh Sundaram

Michael D Nelson

Wei Wu

Dipanjan Sengupta

Mariano Tepper

Shigeki Tomishima

Srikanth T Srinivasan

Theodore L Willke

Randall K Webb

Richard Paul Mangold

Anand S Ramalingam

Vinodh Gopal

Sandeep K Guliani

Piotr Wysocki

Yi Zou

Myron Loewen

Akshay G Pethe

Jason Casmira

Divya Narayanan

Pranav Kalavade

Xin Guo

Albert Fazio

Adrian R Pearson

David B Minturn

Andrew Warrack Morning-Smith

Peng Li

Ningde Xie

Rowel S Garcia

Jackson Ellis

Kelvin D Green

Vasanthi Jagatha

Brian M Yablon

Martin Langhammer

James D Guilford

Kirk S Yap

Mahesh A Iyer

Raj K Ramanujan

Ravi H Motwani

Omesh Tickoo

Ravi Prakash Gutala

Scott J Weber

Zion S Kwok

Andrew W Vogan

Robert W Faber

John Hung

Aravind Raghavendra Dasu

Ilya K Ganusov

Bruce Querbach

Leena K Puthiyedath

Matthew Goldman

August A Camber

Craig J Jahne

Sowmiya Jayachandran

Benjamin Walker

Darren Lasko

William K Lui

Matthew I Adiletta

William K Waller

Scott Burridge

Joerg Hartung

Jason K Yu

Nathaniel G Burke

Jorge Ulises Martinez Araiza

William Chiu

Fred W Nance, Jr

Wing-Gong Lew

Ambika Krishnamoorthy

Jonathan Bryan Stern

Zion Kwok

Terence Magee

Wayne J Allen

Methods and apparatus for sparse column-aware encodings for numeric data types, including integer data and floating-point data (float, double, etc.). The encoding schemes are tailored to take advantage of column addressable memories such as stochastic associative memories (SAM) to enable Stochastic Associative Search (SAS), which is a highly efficient and fast way of searching through a very large database of records (order of Billions) and finding similar records to a given query record (search key). Techniques are also disclosed for performing range searches for both integer and floating-point data types. The integer or float data is converted to Hexadecimal form and encoded using an m-of-n constant weight encoding. Only the columns with set bits in search keys need to be read, which significantly reduces the number of reads required for searches.

Sparse column-aware encodings for numeric data types

A data storage system with a parallel array of dense memory cards and high airflow is described. In one example, a rack-mount enclosure has a horizontal plane board with memory connectors and external interfaces. Memory cards each have a connector to connect to a respective memory connector of the horizontal plane board, each memory card extending parallel to each other memory card from the front of the enclosure and extending orthogonally from the first side of the horizontal plane board. A power supply proximate the rear of the enclosure and the first side of the horizontal plane board provides power to the memory cards through the memory card connectors and has a fan to pull air from the front of the enclosure between the memory cards and to push air out the rear of the enclosure.

Data storage system with parallel array of dense memory cards and high airflow

A memory accessed by rows and/or by columns in which an array of bits can be physically stored physical one-bit wide columns with each bit of the multi-bit wide logical column stored in a one-bit physical column in a different physical die. The multi-bit column is read by reading a one-bit physical column in each of the different physical die in parallel. The multi-bit wide logical column is arranged diagonally across M physical rows and M one-bit physical columns with each bit of the multi-bit wide logical column in the logical row stored in a different physical row and physical one-bit wide column in one of plurality of dies.

Method and apparatus to perform a multiple bit column read using a single bit per column memory accessible by row and/or by column

Examples described herein relate to an apparatus comprising: circuitry to receive a request to store data as a part of a matrix in a memory device; circuitry to allocate address mappings to the data to reduce a number of sequential accesses to a same partition of a portion of the memory device; circuitry to store the address mappings for access with a read operation; and circuitry to cause storage of the data into the memory device according to the address mappings. In some examples, the matrix comprises one or more columns and/or one or more rows. In some examples, the memory device comprises one or more of: a three-dimensional (3D) cross point memory device, volatile memory device, or non-volatile memory device.

Data access ordering for writing-to or reading-from memory devices

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a primary persistent storage with a first type of media and a nonvolatile memory buffer with a second type of media that is different from the first type of media, store metadata for incoming write data in the nonvolatile memory buffer, store other data for the incoming write data in the primary persistent storage, and provide both runtime and power-fail write atomicity for the incoming write data. Other embodiments are disclosed and claimed.

SSD managed host write atomicity with arbitrary transfer length

A memory accessed by rows and/or by columns in which an array of bits can be physically stored in multi-bit wide columns in physically contiguous rows is provided. A multi-bit wide logical column is arranged diagonally across (M/multi-bits) physical rows and (M/multi-bits) physical columns with each of the plurality of multi-bit wide logical columns in the logical row stored in a different physical row and physical multi-bit column.

Method and apparatus to perform a read of a column in a memory accessible by row and/or by column

Technologies for performing random sparse lifting and Procrustean orthogonal sparse hashing using column read-enabled memory include a device that has a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Further, the circuitry is configured to determine a Hamming distance between the search hash code and each of the binary dimensionally expanded vectors.

Technologies for performing sparse lifting and procrustean orthogonal sparse hashing using column read-enabled memory

Examples herein relate to a storage system that separately handles portions of a write operation that are aligned and misaligned with respect to retrievable segments from a storage device. For misaligned portions, a buffer can be used to store misaligned retrievable segments and update the segments with content provided with the write operation. Aligned portions of content associated with a write request can be written directly to the storage medium or overwrite corresponding retrievable segments present in the buffer. A table or array can track logical block addresses that correspond to content in the buffer or in the storage. Content in the buffer can be kept in the buffer without being backed-up or persisted to the storage until a triggering event occurs such as power loss or low space in the buffer.

Buffer to reduce write amplification of misaligned write operations

Technologies for refining stochastic similarity search candidates include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Additionally, the circuitry is configured to identify a result set of the binary dimensionally expanded vectors as a function of a Hamming distance of each binary dimensionally expanded vector from the search hash code and determine, from the result set, a refined result set as a function of a similarity measure in an original input space of the input data vectors.

Technologies for refining stochastic similarity search candidates

A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

Three dimensional circuit systems and methods having memory hierarchies

Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data; and write data to the at least one storage device.

Storage appliance for processing of functions as a service (FaaS)

A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.

Offload defrag operation for host-managed storage

Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.

Error correction for dynamic data in a memory that is row addressable and column addressable

Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

Technologies for performing macro operations in memory

Growing community of inventors

Portland, OR, United States of America

Jawad Basit Khan