Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Jaw-Juinn Horng

Szu-Lin Liu

Yung-Chow Peng

Chin-Ho Chang

Amit Kundu

Chung-Hui Chen

Szu-Chun Tsao

Yi-Wen Chen

Yi-Hsiang Wang

Bei-Shing Lien

Chia-Hsin Hu

Wen-Shen Chou

Sun-Jay Chang

Chung-Peng Hsieh

Po-Zeng Kang

Bindu Madhavi Kasina

Der-Chyang Yeh

Wei-Lin Lai

Po-Yu Lai

Kuo-Feng Yu

Chia-Lin Yu

Wan-Te Chen

Chung-Kai Lin

Ching-Ho Chang

Shih-Cheng Yang

Hui-Zhong Zhuang

Chih-Liang Chen

Fu-Lung Hsueh

Shuo-Mao Chen

Fu-Chih Yang

Chia-Chung Chen

Jen-Hao Yeh

Jinn-Yeh Chien

Ya Yun Liu

Sa-Lly Liu

Tai-cheng Kee

Pang-yen Chin

An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.

Integrated circuit and method for manufacturing the same

A temperature sensor circuit, a control circuit, and a control method are provided. The temperature sensor circuit comprises a temperature sensor and a control circuit. The control circuit is coupled to the temperature sensor and comprises a current source, a sampling circuit, and a computing circuit. The current source is configured to provide a first current and a second current to the temperature sensor in different time periods. The sampling circuit is coupled to the temperature sensor and configured to obtain and store a first voltage information and a second voltage information from the temperature sensor when the first current and second current are respectively provided. The computing circuit is coupled to the sampling circuit and configured to generate a sensing result corresponding to a difference of subtracting the second voltage information from the first voltage information.

Temperature sensor circuits and control circuits and method for temperature sensor circuits

A method (of decoupling from voltage variations in a first voltage drop between first and second reference voltage rails) includes: electrically coupling one or more components to form a decoupling capacitance (decap) circuit; electrically coupling one or more components to form a filtered biasing circuit; and making an unswitched series electrical coupling of the decap circuit and the filtered biasing circuit between the first and second reference voltage rails.

Method of operating decoupling system, and method of fabricating same

A method includes implanting a first dopant having a first dopant type into a substrate to define a plurality of source/drain (S/D) regions. The method further includes implanting a second dopant having the first dopant type into the substrate to define a channel region between adjacent S/D regions of the plurality of S/D regions, wherein a dopant concentration of the second dopant in the channel region is less than half of a dopant concentration of the first dopant in each of the plurality of S/D regions. The method further includes forming a gate stack over the channel region. The method further includes electrically coupling each of the plurality of S/D regions together.

Method of making decoupling capacitor

A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to a ratio between the second AC component signal and the first AC component signal.

Circuit, semiconductor device and method for parameter PSRR measurement

A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.

Bandgap reference circuit

A middle-range (mid) low dropout (LDO) voltage has both sinking and sourcing current capability. The mid LDO can provide a voltage reference in active mode and power mode for core only design to work in a Safe Operating Area (SOA). The output of mid LDO can track IO power and/or core power dynamically. The mid LDO can comprise a voltage reference generator and a power-down controller connected to an amplifier, which output is connected to a decoupling capacitor. The provision of a high ground signal allows the mid LDO provide the sinking and sourcing currents.

Low-dropout (LDO) voltage regulator including amplifier and power down control unit (PDCTRL)

A method of operating a circuit includes providing the circuit, the circuit includes an operational amplifier, a plurality of sampling switches, a plurality of holding switches, and a plurality of combined switches. The method further includes: during a first phase, causing the plurality of sampling switches to be closed, the plurality of the holding switches to be open, and the plurality of combined switches to be open; during a second phase, causing the plurality of combined switches to be closed; during a third phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be open; and during a fourth phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be closed.

Circuit and method to enhance efficiency of semiconductor device

Systems and methods as described herein may take a variety of forms. In an example, a circuit includes a first voltage stepdown module and a second voltage stepdown module. The first voltage stepdown module has a supply voltage and a first reference voltage as inputs, and an intermediate stepped down voltage as an output, the intermediate stepped down voltage being electrically coupled to a feedback input of the first voltage stepdown module. The second voltage stepdown module includes a low-dropout voltage regulator having the intermediate stepped down voltage and a second reference voltage as inputs and a target voltage as an output.

Circuit for outputting a stepdown voltage and method for stepping down a voltage

Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.

Voltage reference temperature compensation circuits and methods

A semiconductor device and a method for a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a core transistor having a drain configured to receive a first voltage, and a first dummy device connected to the drain of the core transistor, the first dummy device having a first dummy transistor and a second dummy transistor. Wherein a gate and a source of the first dummy transistor are connected to each other. Wherein a drain of the second dummy transistor is connected to the source of the first dummy transistor. Wherein a gate of the second dummy transistor is connected to the drain of the core transistor.

Dummy device for core device to operate in a safe operating area and method for manufacturing the same

A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.

Semiconductor devices, semiconductor structures and methods for fabricating a semiconductor structure

Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

Voltage amplifier based on cascaded charge pump boosting

Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.

LDO/band gap reference circuit

A noise detecting circuit including an amplifier circuit amplifying an input signal indicating a noise level of a circuit to be detected and output an amplified signal; a filtering circuit receiving and filtering the amplified signal and output a filtered signal; and a comparing circuit receiving and compare the filtered signal to a reference voltage and output an output signal; wherein the filtering circuit includes: an output terminal; and a first filter selectively coupled to the output terminal, including: a sub-output terminal; a switch selectively coupling the sub-output terminal to the output terminal; a resistor, wherein a terminal of the resistor is coupled to the amplifier circuit and another terminal of the resistor is coupled to the sub-output terminal; and a capacitor, wherein a terminal of the capacitor is coupled to the sub-output terminal and another terminal of the capacitor is coupled to a reference voltage source.

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Hsinchu, Taiwan

Jaw-Juinn Horng