Motorola Corporation

Javier Saldana

Oded Yishay

Joseph Jelemensky

Kelvin E McCollough

Ann E Harwood

Pamela Daniel

Under software control, a loss of clock detect circuit (24) can be enabled to detect loss of clock. A plurality of different clock signals, including the input reference clock (34) to the PLL (12) and the feedback (36) from the PLL (12), are monitored by the loss of clock circuit (24). When the currently selected system clock (38) signal is lost, a control circuit (28) can select an optimal back-up clocking mode based on which clock signals were lost. One such selectable mode is to utilize the input reference clock (34) directly instead of the PLL (12). Another such selectable mode is to utilize the PLL (12) in a self-clocked mode to provide the system clock (38).

Method and apparatus for managing failure of a system clock in a data

Method and apparatus for performing multiplexed and non-multiplexed bus cycles in a data processing system (10). The present invention allows a data processing system (10) to switch from multiplexed bus cycles to non-multiplexed bus cycles, and vice-versa, without requiring the data processing system (10) to be reset. In one embodiment of the present invention, a single user programmable control bit (90) is used to select whether an external bus cycle will be multiplexed or non-multiplexed. In more complex embodiments of the present invention, the ability to switch between multiplexed external bus cycles and non-multiplexed external bus cycles may be achieved by way of a plurality of user programmable register fields (96, 100, 102, and 104) located in registers 44. The plurality of user programmable register fields (96, 100, 102, and 104) may be associated with one or more chip select signals.

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Austin, TX, United States of America

Javier Saldana