Compaq Computer Corporation, Inc.

Hewlett-Packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Javier F Izquierdo

Paul R Culley

John A Landry

Kenneth A Jansen

Mark E Taylor

David A Miller

Thanh Thien Tran

Clarence Y Mar

Tahir Cader

Hai Ngoc Nguyen

John S Thayer

Dale J Mayer

Ronald D Noblett

Ameya Soparkar

Mark Joseph Lepore

Harry R Rogers, Jr

An example system is provided herein. The system includes a fuel cell coupled to the set of electronic components. The fuel cell provides power to the set of electronic components when a set of conditions are met.

Fuel cell to power electronic components

Power distribution to computer systems. At least some of the illustrative embodiments are systems including a power supply configured to convert an alternating current (AC) power signal to a direct current (DC) power signal (and the power supply comprising a first power port and a second power port, the second power port different than the first power port), a first computer system coupled to the first power port (the power supply configured to provide DC operational power to the first computer system through the first power port, and the first computer system the only computer system receiving operational power through the first power port), and a second computer system different than the first computer system (the power supply configured to provide DC operational power to the second computer system through the second power port, and the second computer system the only computer system receiving power from the second power port).

Power distribution to computer system

A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.

Multiprocessor communication using reduced addressing lines

Multiprocessor system including interprocessor encoding and decoding

A multiprocessor system includes first and second processing units. Each of these processing units includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. Each processing unit is reset in response to a system reset signal but only selected portions of the processing units are reset in response to a partial-reset signal. The system can also include a number other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.

Multi-processor system with system wide reset and partial system reset

A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.

Method and apparatus for independently resetting processors and cache

A clock signal is distributed over a circuit board and across a connector as a sine wave. A circuit located near the clocked circuitry converts the sine wave into a same frequency square wave for use by the clocked circuitry. The output stage of the converter circuitry provides a high output level to drive CMOS circuitry. The output transistor is pulled up to 5 volts, but the preceding transistors are pulled up to 6.3 volts so that the base to emitter drops are compensated.

High frequency clock signal distribution with high voltage output

A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.

Memory accessing system with an interface and memory selection unit

An apparatus for determining system configuration in a computer system using only one 8 bit data port. Permanent connections on each of the microprocessor and memory boards provide respective configuration and/or memory information about each board. The signals are stored in serial out shift registers associated with each board that are daisy chained together. These shift registers serially transmit the configuration information to one 8 bit data port, which then transmits this information to the computer system in 8 bit increments. If a given slot is empty it is automatically bypassed in the shift register daisy chain.

Growing community of inventors

Houston, TX, United States of America

Javier F Izquierdo