Arm Limited

Javier Diaz Bruguera

David Raymond Lutz

Neil Burgess

David M Russinoff

The present disclosure relates generally to arithmetic units of processors, and may relate more particularly to multi-cycle division operations. Multiple-cycles of a radix-m division operation may be performed to generate one or more signal states representative of a result value based at least in part on a dividend value and a divisor value.

Method, system and device for multi-cycle division operation

A data processing apparatus is provided to convert a plurality of signed digits to an output value, the data processing apparatus comprising: receiver circuitry to receive, at each of a plurality of iterations, a signed digit from the plurality of signed digits, and previous intermediate data. Conversion circuitry performs a negative-output conversion from the signed digit to an unsigned digit, such that the output value comprising the unsigned digit is negative. Concatenation circuitry concatenate bits of the unsigned digit and bits of the previous intermediate data to produce updated intermediate data and output circuitry provides the updated intermediate data as the previous intermediate data of a next iteration. After the plurality of iterations, the output circuitry outputs at least part of the updated intermediate data as the output value.

Conversion circuitry

A data processing apparatus is provided to convert a plurality of signed digits to an output value. Receiver circuitry receives, at each of a plurality of iterations, one of the plurality of signed digits, each of the signed digits comprising a number of bits dependent on a radix. The signed digits being used to form an unrounded output value followed by zero or more extra bits. Adjustment circuitry adjusts a least-significant digit of the unrounded output value to produce an incremented unrounded output value after the plurality of iterations. Rounding circuitry selects from among the unrounded output value and the incremented unrounded output value to produce the output value. The adjustment circuitry is adapted, when a value of a position of a least-significant bit of the unrounded output value is greater than or equal to the radix divided by two, to adjust a subset of the digits of the unrounded output value.

Apparatus and method for rounding

A data processing apparatus is provided, for performing a digit-recurrence square root operation on an input value. Receiver circuitry receives a remainder value of a previous iteration of the digit-recurrence square root operation. Comparison circuitry compares most significant bits of the remainder value of the previous iteration with a number of selection constants, in order to output a next digit of a result of the digit-recurrence square root operation. The comparison circuitry compares at most 3 fractional bits of the remainder value of the previous iteration with the plurality of selection constants.

Square root digit recurrence

An apparatus has processing circuitry comprising an L&#xd7;M multiplier array. An instruction decoder associated with the processing circuitry supports a multiply-and-accumulate-product (MAP) instruction for generating at least one result element corresponding to a sum of respective E&#xd7;F products of E-bit and F-bit portions of J-bit and K-bit operands respectively, where 1&#x3c;E&#x3c;J&#x2264;L and 1&#x3c;F&#x3c;K&#x2264;M. In response to the MAP instruction, the instruction decoder controls the processing circuitry to rearrange F-bit portions of the second K-bit operand to form a transformed K-bit operand, and to control the L&#xd7;M multiplier array in dependence on the first J-bit operand and the transformed K-bit operand to add the respective E&#xd7;F products using a subset of the adders used for accumulating partial products for a conventional multiplication.

Multiply-and-accumulate-products instructions

A data processing apparatus comprises signal receiving circuitry to receive a signal corresponding to a divide instruction that identifies a dividend x and a divisor d. Processing circuitry performs, in response to said divide instruction, a radix-N division algorithm to generate a result value q=x/d, where N is an integer power of 2 and greater than 1. Said division algorithm comprises a plurality of iterations, each of said plurality of iterations being performed by quotient digit calculation circuitry to determine a quotient value of that iteration q[i+1] based on a remainder value of a previous iteration rem[i]; and remainder calculation circuitry to determine a remainder value of that iteration rem[i+1] based on said quotient value of that iteration q[i+1] and said remainder value of said previous iteration rem[i]. Result calculation circuitry derives said result value q based on each quotient value selected by said digit selection circuitry for each of said plurality of iterations. For at least some of said plurality of iterations, said quotient digit calculation circuitry speculatively determines a set of candidate values before a quotient value of said previous iteration is known and, in response to said quotient value of said previous iteration becoming known, determines said quotient value of that iteration q[i+1] based on one of said candidate values.

Circuitry and method for performing division

A data processing apparatus is provided to perform a digit-recurrence division operation to determine a quotient as a result of dividing a dividend by a divisor. Scaling circuitry scales the dividend and the divisor by a factor to produce a scaled dividend and a scaled divisor. Digit recurrence circuitry performs one or more iterations of the digit-recurrence division operation on the scaled dividend and the scaled divisor, with each iteration producing a digit of the quotient and a remainder value. The remainder value is provided as an input to the digit recurrence circuitry for a subsequent iteration. Initialization circuitry performs a first iteration of the one or more iterations and provides the digit of the quotient after the first iteration. The initialization circuitry receives, as an input, an intermediate value produced by the scaling circuitry while scaling the dividend.

Digit recurrence division with scaling and digit selection using intermediate value

A data processing apparatus is provided, to calculate an at least partial square root of a floating point number having an exponent and significand. Recurrence circuitry performs one or more iterations of an iterative square root operation, each of the one or more iterations receiving an input at least partial square root and an input remainder to produce the at least partial square root and a remainder of performing the iterative square root operation. The recurrence circuitry provides the at least partial square root and the remainder as the input at least partial square root and the input remainder for a subsequent iteration of the iterative square root operation. The recurrence circuitry includes initialization circuitry to provide the at least partial square root and the remainder after at least an initial iteration of the one or more iterations. The initialization produces the remainder by performing a selection of one of a plurality of predetermined values in dependence on whether the exponent is odd or even.

Partial square root calculation

A data processing apparatus for performing rounding on an input value to produce a rounded form output value includes floor calculation circuitry that receives the input value in redundant-representation and generates two candidates of a floor of the input value in non-redundant representation. Ceiling calculation circuitry receives the input value in redundant-representation and generates two candidates of a ceiling of the input value in non-redundant representation. Selection circuitry outputs one of the two candidates of the floor of said input value and the two candidates of the ceiling of said input value as the rounded form output value, based on a sign of a residual value associated with the input value. Each of the two candidates of the floor of the input value correspond with different values of the sign of the residual value and each of the two candidates of the ceiling of said input value correspond with different values of the sign of said residual value.

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Austin, TX, United States of America

Javier Diaz Bruguera