Esilicon Corporation

Javier DeLaCruz

A 3DIC includes a die and a substrate. The die includes multiple bumps to provide electrical connection the substrate. The substrate includes multiple elongated contact pads. The elongated contact pads making electrical contact with the bumps and shaped to maintain alignment with the bumps over a temperature range.

Elongated pad structure

Disclosed is a probe card for testing a wireless module on an integrated circuit die contained on a wafer. The probe card includes a connector and a plurality of probes. The connector connects the probe card to test equipment. The plurality of probes connects the probe card to a wafer containing a plurality of integrated circuit dies. The probe card additionally includes an antenna configured to transmit a wireless test signal to be received by at least one of the integrated circuit dies, and/or to receive a wireless signal transmitted by at least one of the integrated circuit dies.

Wireless probes

A memory interface architecture uses a serializer/deserializer (SerDes) to connect a memory array on one semiconductor die to a device on another semiconductor die, for example via a fast interposer.

Communication interface architecture using serializer/deserializer

A silicon interposer with redundant thru-silicon vias. The silicon interposer includes a first trace structure on a first side of the interposer and a second trace structure on a second side of the interposer. The silicon interposer also includes at least two redundant thru-silicon vias connecting the first trace structure to the second trace structure.

Parallel signal via structure

A system and a method for testing thru silicon vias (TSVs) in a silicon die. A silicon die containing multiple TSVs is mounted on a wafer tape. Two probe points are probed on the exposed side of the silicon die. A resistance is measured between the two probe points and an electrical integrity is determined based on the measured resistance.

Testing of thru-silicon vias

An integrated circuit with probeable and routable interfaces is disclosed. The integrated circuit includes multiple micro-pillars that are attached to the surface of the integrated circuit, and multiple macro-pillars also attached to the surface of the integrated circuit. The micro-pillars provide an electrical interface to the integrated circuit during regular operation. The macro-pillars provide an electrical interface to the integrated circuit both during regular operation and during testing of the integrated circuit.

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Summit, NJ, United States of America

Javier DeLaCruz